Mitsubishi Q00JCPU User Manual page 858

APPENDICES
Number Name Meaning
Maximum
number of
blocks used for
dedicated
instruction of
SD796
Multiple CPU
high speed
transmission
setting (for CPU
No.1)
Maximum
number of
blocks used for
dedicated
instruction of
SD797
Multiple CPU
Maximum number
high speed
of blocks used for
transmission
dedicated
setting (for CPU
instruction range 1
No.2)
to 7 (Default: 2)
* When value
Maximum
other than 1 to 7
number of
is set, operation
blocks used for
is performed as if
dedicated
7 is set.
instruction of
SD798
Multiple CPU
high speed
transmission
setting (for CPU
No.3)
Maximum
number of
blocks used for
dedicated
instruction of
SD799
Multiple CPU
high speed
transmission
setting (for CPU
No.4)
*14: The Universal model QCPU except the Q02UCPU.
*15: For the Q03UDCPU, Q04UDHCPU, Q06UDHCPU whose first 5 digits of the serial number are "10011" or earlier, the range is 1 to 9 (Default: 2) and when a
value other than 1 to 9 is set, operation is performed as if 9 is set.
App
- 69 Appendix 2 Special Register List
TableApp.25 Special register
Explanation
• Specifies the maximum number of blocks used for the dedicated
instruction of Multiple CPU high speed transmission (target CPU = CPU
No.1). When the dedicated instruction of Multiple CPU high speed
transmission is executed to the CPU No.1, and the number of empty
blocks of the dedicated instruction transmission area is less than the
setting value of this register, SM796 is turned ON, which is used as the
interlock signal for consecutive execution of the dedicated instrucion of
Multiple CPU high speed transmission.
• Specifies the maximum number of blocks used for the dedicated
instruction of Multiple CPU high speed transmission (target CPU = CPU
No.2). When the dedicated instruction of Multiple CPU high speed
transmission is executed to the CPU No.2, and the number of empty
blocks of the dedicated instruction transmission area is less than the
setting value of this register, SM797 is turned ON, which is used as the
interlock signal for consecutive execution of the dedicated instrucion of
Multiple CPU high speed transmission.
• Specifies the maximum number of blocks used for the dedicated
instruction of Multiple CPU high speed transmission (target CPU = CPU
No.3). When the dedicated instruction of Multiple CPU high speed
transmission is executed to the CPU No.3, and the number of empty
blocks of the dedicated instruction transmission area is less than the
setting value of this register, SM798 is turned ON, which is used as the
interlock signal for consecutive execution of the dedicated instrucion of
Multiple CPU high speed transmission.
• Specifies the maximum number of blocks used for the dedicated
instruction of Multiple CPU high speed transmission (target CPU = CPU
No.4). When the dedicated instruction of Multiple CPU high speed
transmission is executed to the CPU No.4, and the number of empty
blocks of the dedicated instruction transmission area is less than the
setting value of this register, SM799 is turned ON, which is used as the
interlock signal for consecutive execution of the dedicated instrucion of
Multiple CPU high speed transmission.
Corres-
ponding
Set by Corresponding
ACPU
(When Set)
D9
U (At 1 scan
New
after RUN)
U (At 1 scan
New
after RUN)
U (At 1 scan
New
after RUN)
U (At 1 scan
New
after RUN)
CPU
*14*15
QnU
*14*15
QnU
*14*15
QnU
*14*15
QnU