Page 3 ! SAFETY CAUTIONS ! (You must read these cautions before using the product) In connection with the use of this product, in addition to carefully reading both this manual and the related manuals indicated in this manual, it is also essential to pay due attention to safety and handle the product correctly.
Page 4 Chemicals, Mining and Drilling, and/or other applications where there is a significant risk of injury to the public or property. Notwithstanding the above, restrictions Mitsubishi may in its sole discretion, authorize use of the PRODUCT in one or more of the Prohibited Applications, provided that the usage of the PRODUCT is limited only for the...
Page 5 This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual.
Page 6 *The manual number is given on the bottom left of the back cover. Print Date *Manual Number Revision Dec., 2009 IB (NA) 66250-I Correction Section 3.5, 3.8.1, 5.3.1, 6.4.3, 7.1.1, 7.1.2, 7.1.3, 7.1.4, 7.3.1, 7.4.1, 7.4.6, 7.6.1, 7.6.2, 7.6.3, 7.6.4, 7.6.5, 7.6.6, 7.8.2, 9.1, 9.2, 9.3, 9.4, 9.5, 9.6, APP 1.1, APP 1.2, APP 1.3, APP 1.4 Addition CONDITIONS OF USE FOR THE PRODUCT...
Page 7 INTRODUCTION Thank you for choosing the Mitsubishi MELSEC-A Series of General Purpose Programmable Controllers. Please read this manual carefully so that the equipment is used to its optimum. A copy of this manual should be forwarded to the end User.
Page 8: Table Of Contents
CONTENTS INTRODUCTION ........................1 − 1 ~ 1 − 3 INSTRUCTIONS ........................2 − 1 ~ 2 − 24 Classification..........................2 − 1 Instruction List..........................2 − 2 Explanation for instructions lists ..................2 − 2 2.2.1 Sequence instructions ....................2 − 5 2.2.2 Basic instructions......................2 − 8 2.2.3 Application instructions ....................2 −...
Page 9 Output Instructions........................5 − 14 Bit device, timer, counter output (OUT) ...............5 − 14 5.3.1 Bit device set, reset (SET,RST) ...................5 − 19 5.3.2 Edge-triggered differential output (PLS, PLF)..............5 − 23 5.3.3 Bit device output reverse (CHK) ..................5 − 26 5.3.4 Shift Instructions ........................5 −...
Page 10 Program Branch Instructions ....................6 − 58 Conditional jump, unconditional jump (CJ, SCJ, JMP) ..........6 − 58 6.5.1 Subroutine call, return (CALL, CALLP, RET) ...............6 − 62 6.5.2 Interrupt enable, disable, return (EI, DI, IRET) ............6 − 65 6.5.3 Microcomputer program call (SUB, SUBP)..............6 − 68 6.5.4 Program Switching Instructions ....................6 −...
Page 11 Special function module 1-, 2-word data read (FROM, FROMP, DFRO, DFROP) ..7 − 65 7.6.1 Special function module 1-, 2-word data write (TO, TOP, DTO, DTOP).......7 − 68 7.6.2 7.6.3 Remote terminal module 1- and 2-word data read (FROM, PRC, FROMP, PRC, DFRO, PRC, DFROP, PRC) .........7 − 71 7.6.4 Remote terminal module 1- and 2-word data write (TO, PRC, TOP, PRC, DTO, PRC, DTOP, PRC) ............7 −...
Page 12 ERROR CODE LIST.......................9 − 1 ~ 9 − 39 Reading Error Codes ........................9 − 1 Error Code List for the An, AnN, A3H, A3M, A3V, A0J2H, AnS, A2C, A73, A52G, A1FX and A3N board............................9 − 1 Error Code List for the AnSHCPU ....................9 − 6 Error Code List for the AnACPU and A3A Board ..............
Page 13 MEMO A − 11...
Page 14: Introduction
The parameters of CPU are set to default values. If the default can be used for the purpose, it is not necessary to set the parameter. The user’s programs for the MELSEC-A series PCs are classified as follows. ACPU Programming Manual (fundamental) gives the programs which can be used for CPUs.
Page 15 1. INTRODUCTION MELSEC-A Table 1.1 Applicable CPUs and the Abbreviations Used in This Manual Abbreviations used in this manual Applicable CPUs A1CPU(P21/R21) A2(-S1) A2CPU(P21/R21), A2CPU(P21/R21)-S1 A3CPU(P21/R21) A1NCPU(P21/R21) A2N(-S1) A2NCPU(P21/R21), A2NCPU(P21/R21)-S1 A3NCPU(P21/R21) A3HCPU(P21/R21) A3MCPU(P21/R21) A3VCPU(P21/R21) A2A(-S1) A2ACPU(P21/R21), A2ACPU(P21/R21)-S1 A3ACPU(P21/R21) A0J2H A0J2HCPU(P21/R21) A1SCPU, A1SCPU-S1, A1SCPUC24-R2, A1SJCPU, A1SJCPU-S3 A2SCPU, A2SCPU-S1 A1SH...
Page 16 1. INTRODUCTION MELSEC-A Also refer to the following manuals for writing programs for the A series PCs. Topic Content Reference Manual • Memory capacity and the number of devices of the CPU module. CPU specifications • Specifications of power supply modules, base units, etc.
Page 17: Instructions
2. INSTRUCTIONS MELSEC-A 2. INSTRUCTIONS 2.1 Classification The instructions of MELSEC-A series are largely classified into sequence instruc-tions, basic instructions, and application instructions. These instructions are shown in Table 2.1. Table 2.1 Classification of Instructions Classification of instructions Description page...
Page 18: Instruction List
2. INSTRUCTIONS MELSEC-A 2.2 Instruction List 2.2.1 Explanation for instructions lists Instruction lists in Section 2.2.2 to 2.2.4 are in the following format. Table 2.2 Explanation for Instructions Lists Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol...
Page 19 2. INSTRUCTIONS MELSEC-A 3)….. Indicates the instruction symbol used for the program. The instruction symbol is shown on a 16-bit instruction basis. The symbols of a 32-bit instruction and an instruction executed only at the rise from OFF to ON are as indicated below: 32-bit instruction………D is added to the head of instruction.
Page 20 2. INSTRUCTIONS MELSEC-A 6)….. Indicates the execution condition of each instruction and details are as described below: Symbol Execution Condition Instruction which is always executed regardless of ON/OFF of the preceding condition. No entry If the preceding condition is OFF, that instruction executes an OFF processing. Instruction which is executed during ON.
Page 21: Sequence Instructions
2. INSTRUCTIONS MELSEC-A 2.2.2 Sequence instructions (1) Contact instructions Table 2.3 Contact Instructions Execu- Classi- Instruction Symbol Contents of Processing Applicable CPU Page tion Con- fication Symbol dition Logical operation start (NO contact operation start) Logical NOT operation start (NC contact operation start) Logical product (NO contact series connection) ...
Page 22 2. INSTRUCTIONS MELSEC-A (3) Output instructions Table 2.5 Output instructions Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition Device output 5-14 Device set 5-19 Device reset 5-19  Generates one-program cycle pulses on the leading edge of input 5-23 signal.
Page 23 2. INSTRUCTIONS MELSEC-A (6) Termination instructions Table 2.8 Termination Instructions Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition Always used at the end of the main  FEND routine program to 5-34 terminate processing. Program Always used at the end of the ...
Page 24: Basic Instructions
2. INSTRUCTIONS MELSEC-A 2.2.3 Basic instructions (1) Comparison instructions Table 2.10 Comparison Operation Instructions (Continue) Execu- Classi- Instruction Symbol Contents of Processing Applicable CPU Page tion Con- fication Symbol dition Continuity when (S1) = (S2) AND= Non-continuity when (S1) ≠ (S2) LD<>...
Page 25 2. INSTRUCTIONS MELSEC-A Table 2.10 Comparison Operation Instructions Classi- Execu- fication Instruction Symbol Contents of Processing Applicable CPU Page tion Con- Symbol dition LDD= Continuity when (S1+1, S1) = (S2+1, S2) ANDD= Non-continuity when (S1+1, S1) ≠ (S2+1, S2) ORD= LDD<>...
Page 26 2. INSTRUCTIONS MELSEC-A (2) Arithmetic operation instruction Table 2.11 Arithmetic Operation Instruction (Continue) Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition 6-10 (D) + (S) → (D) 6-10 6-10 (S1) + (S2) → (D) 6-10 16-bit addition/...
Page 27 2. INSTRUCTIONS MELSEC-A Table 2.11 Arithmetic Operation Instruction (Continue) Execu- Classi- Instruction Symbol Contents of Processing Applicable CPU Page tion Con- fication Symbol dition ∗ 6-19 (S1+1, S1) × (S2+1, S2) → (D+3, D+2, D+1, D) ∗ 6-19 32bit multipli- cation/ 6-19 division...
Page 28 2. INSTRUCTIONS MELSEC-A Table 2.11 Arithmetic Operation Instructions Execu- Classi- Instruction Symbol Contents of Processing Applicable CPU Page tion Con- fication Symbol dition ∗ 6-28 (S1) × (S2) → (D+1, D) ∗ 6-28 4-digit multipli- cation, 6-28 division (S1) / (S2) → Quotient (D) |Remainder (D+1) 6-28 ∗...
Page 29 2. INSTRUCTIONS MELSEC-A (3) BCD ↔ BIN conversion instructions Table 2.12 BCD ↔ BIN Conversion Instructions Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition BCD conversion 6-39 BIN (0 to 9999) BCDP 6-39 conver- sion DBCD...
Page 30 2. INSTRUCTIONS MELSEC-A Table 2.13 Data Transfer Instructions Execu- Classi- Instruction Symbol Contents of Processing Applicable CPU Page tion Con- fication Symbol dition BMOV 6-52 BMOVP 6-52 Block transfer FMOV 6-52 FMOVP 6-52 6-56 (D1) ↔ (D2) XCHP 6-56 change DXCH 6-56 (D1+1, D1) ↔...
Page 31 2. INSTRUCTIONS MELSEC-A (6) Program switching instruction Table 2.15 Program Switching Instruction Execu- Classi- Instruction Symbol Contents of Processing Applicable CPU Page tion Con- fication Symbol dition A3H, A3M, A3A Not applicable to AnS, AnSH, A1FX, Switch- Switches between the main and A1, A2(S1), A1N, A2N(S1), 6-70 subprograms.
Page 32: Application Instructions
2. INSTRUCTIONS MELSEC-A 2.2.4 Application instructions (1) Logical operation instructions Table 2.17 Logical Operation Instructions Execu- Classi- Instruction Symbol Contents of Processing Applicable CPU Page tion Con- fication Symbol dition WAND (D) AND (S) → (D) WANDP WAND Logical product (S1) AND (S2) →...
Page 33 2. INSTRUCTIONS MELSEC-A Table 2.17 Logical Operation Instructions (Continue) Execu- Classi- Instruction Symbol Contents of Processing Applicable CPU Page tion Con- fication Symbol dition WXNR 7-16 (D) XOR (S) → (D) WXNRP 7-16 WXNR 7-16 exclu- (S1) XOR (S2) → (D) sive logical WXNRP...
Page 34 2. INSTRUCTIONS MELSEC-A (2) Rotation instructions Table 2.18 Rotation Instructions Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition Carry 7-23 RORP "n" bit rotation to right 7-23 Right ward rotation Carry 7-23 RCRP 7-23 "n"...
Page 35 2. INSTRUCTIONS MELSEC-A (3) Shift instructions Table 2.19 Shift Instructions Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition 7-32 SFRP 7-32 n bit shift 7-32 SFLP 7-32 BSFR 7-35 BSFRP 7-35 1 bit shift BSFL 7-35...
Page 36 2. INSTRUCTIONS MELSEC-A (4) Data processing instructions Table 2.20 Date Processing Instructions Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition (S2) 7-41 (S1) Date search A0 : Coinciding number SERP 7-41 A1 : Coinciding quantity 7-43 SUMP 7-43...
Page 37 2. INSTRUCTIONS MELSEC-A (5) FIFO instructions Table 2.21 FIFO Instructions Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition FIFW 7-60 Write FIFWP 7-60 FIFR 7-60 Read FIFRP 7-60 (6) Buffer memory Access instructions Table 2.22 Buffer Memory Access Instruction (Continue) Execu- Classi-...
Page 38 2. INSTRUCTIONS MELSEC-A Table 2.22 Buffer Memory Access Instructions Execu- Classi- Instruction Symbol Contents of Processing Applicable CPU Page tion Con- fication Symbol dition  Dedicated to A2C and A52G. 7-76  Dedicated to A2C and A52G. 7-76 Date Writes data from remote write terminals.
Page 39 2. INSTRUCTIONS MELSEC-A (9) Display instructions Table 2.25 Display Instructions Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition Outputs ASCII codes (16 charac- ters) from the specified devices Not applicable to A2C and A52G. 7-106 (8 points) to the output module.
Page 40 2. INSTRUCTIONS MELSEC-A (11) Instruction for servo programs Table 2.27 Instructions for Servo Programs Execu- Classi- Instruction Symbol Contents of Processing tion Con- Applicable CPU Page fication Symbol dition Start  DSFRP Requests start of servo programs. Dedicated to A73. 7-140 request Changes present position data of...
Page 41: Instruction Structure
3. INSTRUCTION STRUCTURE MELSEC-A 3. INSTRUCTION STRUCTURE 3.1 Instruction Structure 1) Many instructions may be divided into an instruction part and a device as follows: Instruction part…….. Indicates the function. Device……………… Indicates the data for use with that instruction. 2) The instruction structure may be largely classified as follows with the instruction part and device(s) combined: a) Instruction part …….
Page 42: Instruction Structure
3. INSTRUCTION STRUCTURE MELSEC-A (1) Source (S) 1) Source data is used for operation. 2) Source data depends on the device specified as follows: • Constant …………………… Specify the numeric value used for the operation. This value is set while the program is being written and cannot be changed during run of the program.
Page 43: Bit Processing
3. INSTRUCTION STRUCTURE MELSEC-A 3.2 Bit Processing Bit processing is performed when a bit device (X, Y, M, L, S, B, F) has been specified. Either of 1-bit processing or digit specification processing with 16-bit or 32-bit instructions may be selected. 3.2.1 1-bit processing When the sequence instruction is used, more than one bit (one point) cannot be specified for the bit device.
Page 44 3. INSTRUCTION STRUCTURE MELSEC-A Ladder Example Processing 16-bit instruction X010 P K1 X000 Source (S) data Fig. 3.2 Ladder Example and Processing (b) When there is digit specification on the destination (D) side, the number of points set by the digit specification is used on the destination side. Circuit Example Processing Source (S) data is numeric value...
Page 45 3. INSTRUCTION STRUCTURE MELSEC-A (3) When there is digit specification on the source (S) side, the range of numeric values handled as source data are as shown in Table 3.2. Table 3.2 List of Digit Specification and Handled Numeric Values Specified Number Specified Number 32-Bit Instruction...
Page 46: Handling Of Numeric Values
3. INSTRUCTION STRUCTURE MELSEC-A 3.3 Handling of Numeric Values In the A series, there are instructions which handle numeric values in 16 bits and 32 bits. The highest bits of 16 bits and 32 bits are used for the judgement of positive and negative.
Page 47 3. INSTRUCTION STRUCTURE MELSEC-A When the range of numeric values handled in 16 bits and 32 bits exceeds that specified (overflow, underflow) this is indicated as in the following table. Table 3.3 processing Outside the Allowed Numeric Value Range Processing of 16-bit Data Processing of 32-bit Data Decimal display Hexadecimal display...
Page 48: Storing 32-Bit Data
3. INSTRUCTION STRUCTURE MELSEC-A 3.4 Storing 32-bit Data 32-bit data is stored using digit specification of K1 to 8 when it is stored in bit devices or using two consecutive words when it is stored in word devices. (1) Storing data in bit devices Refer to Section 3.2.2 (2).
Page 49 3. INSTRUCTION STRUCTURE MELSEC-A 2) Index registers can process 32-bit instructions when Z and V are used in pairs. In this case, Z is regarded as the lower 16-bit device, and therefore, V cannot be used in a 32-bit instruction. (Programs cannot be entered.) X010 HA78D8ED...
Page 50: Index Qualification
3. INSTRUCTION STRUCTURE MELSEC-A 3.5 Index Qualification (1) The index qualification is used to specify the device number be providing an index (Z, V) to the device and adding the specified device number and index content. (2) The index qualification can be used for devices X, Y, M, L, S, B, F, T, C, D, R, W, K, H, and P.
Page 51 3. INSTRUCTION STRUCTURE MELSEC-A (5) In the following cases, the basic instruction and application instruction result in operation error. (a) When the index qualification is performed and the device range has been exceeded. In this case, however, K and H are excluded. Index Circuit Example Judgement...
Page 52: Subset Processing
3. INSTRUCTION STRUCTURE MELSEC-A 3.6 Subset Processing Subset processing is used to increase processing speed provided with the following conditions when bit devices are specified in basic or application instructions. Instruction symbols are same as those of normal processings. Table 3.4 Conditions for Subset Processing CPU Type Index Qualification Bit Device...
Page 53 3. INSTRUCTION STRUCTURE MELSEC-A (2) Error processing If an operation error has occurred during the execution of basic instructions or application instructions, the error flag (M9010, 9011) is turned on and the error step number is stored into the error step storage register (D9010, 9011). *M9010……….Turned on by operation error and turned off when the next basic instruction or application instruction is valid.
Page 54: Cautions On Using Ana, A2As, Anu, Qcpu-A (A Mode) And A2Ush Board
3. INSTRUCTION STRUCTURE MELSEC-A 3.8 Cautions on Using AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board This section gives the cautions to be exercised when AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board is used. 3.8.1 The number of steps used in instructions (1) The number of steps increases by one every time a device assigned as shown below (device extended by AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board) is used in each instruction.
Page 55 3. INSTRUCTION STRUCTURE MELSEC-A T1000 T1000………………..1+1=2 steps D2000 W010 D2000 W010Z1……5+1+1=7 steps Extension device Extension device Total 9 steps T0…………………….1 step D2000 D300 D2000Z1 D300 …. 5+1=6 steps Total 7 steps Extension device (2) If index qualification is used in a 1-step sequence instruction (such as LD, OUT), the number of steps increases one.
Page 56: Instructions Of Variable Functions
3. INSTRUCTION STRUCTURE MELSEC-A 3.8.2 Instructions of variable functions The following instructions vary in content of processing when used in the dedicated instructions blocks for the AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board. For details, refer to the AnSHCPU/AnACPU/AnUCPU Programming Manual (Dedicated Instructions).
Page 57: Set Values For The Extension Timer And Counter
3. INSTRUCTION STRUCTURE MELSEC-A 3.8.3 Set values for the extension timer and counter Set values for the timer and counter, shown below, (extended by the AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board) used for the OUT instruction devices should be set with the devices (D, W or R) specified by parameters.
Page 58 3. INSTRUCTION STRUCTURE MELSEC-A (2) Turn-on/off instruction operations at index qualification When the turn-on/off instructions (PLS, PLF, SETF , RSTF P) are designated with index qualification when an AnA, A2AS, AnU, QCPU-A (A Mode) or A2USH board is used, the instructions are executed only when the execution condition for the turn-on/off execution instruction is established.
Page 59 3. INSTRUCTION STRUCTURE MELSEC-A Cautions when a PLS instruction with Index / Startup execution instruction is used in a FOR-NEXT. When a device which functions as a conditions for execution of the PLS instruction / Startup execution command starts up, the PLS command / Startup execution instruction is executed.
Page 60: Storing 32-Bit Data In Index Registers
3. INSTRUCTION STRUCTURE MELSEC-A 3.8.5 Storing 32-bit data in index registers It is possible to store 32-bit data in the index registers (Z1 to Z6, V1 to V6) extended by the AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board. The following index registers are used in pairs to store 32-bit data.
Page 61: Operation When The Out Instruction, Set/Rst Instruction And Pls/Plf Instruction Are From The Same Device
3. INSTRUCTION STRUCTURE MELSEC-A 3.9 Operation when the OUT Instruction, SET/RST Instruction and PLS/PLF Instruction are from the Same Device Here, operation in the case that there is multiple execution of the OUT instruction, SET/RST instruction and PLS/PLF instruction during 1 scan using the same device. (1) In the case of the OUT instruction from the same device.
Page 62 3. INSTRUCTION STRUCTURE MELSEC-A (2) If the SET/RST instruction is used from the same device. (a) The SET instruction turns On the specified device when the SET command goes On and when the SET command goes Off, there is no processing. For this reason, when the SET instruction is executed multiple times in 1 scan from the same device, if even one SET command goes On, the specified device goes On.
Page 63 3. INSTRUCTION STRUCTURE MELSEC-A (3) If the PLS instruction is used from the same device. The PLS instruction turns the specified device On when the PLS command goes from Off to On, and when the PLS command is not going from Onto Off (Off → Off, On →...
Page 64 3. INSTRUCTION STRUCTURE MELSEC-A • When the Off → On of X0 and X1 are the same timing. M0 goes On because X1 is Off M0 goes Off because X1 is On. (M0 remains in the On state.) not Off On.
Page 65 3. INSTRUCTION STRUCTURE MELSEC-A [Timing Chart] • When the On/Off timing of X0 and X1 differ (the specified device does not go On in 1 scan) M0 goes Off because X1 is M0 goes Off because X1 is not On Off.
Page 66: Instruction Format
4. INSTRUCTION FORMAT MELSEC-A 4. INSTRUCTION FORMAT The explanations of instructions given in the following sections use the format described in this section. A0J2H Applicable AnN-F AnA-F board Remark 7.3.3 n-word data 1-word right shift, leftshift (DSFR, DSFRP, DSFL, DSFLP) Available Device Bit device Word (16-bit) device...
Page 67 4. INSTRUCTION FORMAT MELSEC-A Program Examples DSFR Program which shifts the contents of D683 to 689 to the right when XB turns on. • Coding D683 DSFRP DSFRP D683 Specification range of DSFRP instruction Before execution After execution DSFL Program which shifts the contents of D683 to 689 to the left when XB turns on. •...
Page 68 4. INSTRUCTION FORMAT MELSEC-A Explanations Indicates section number, and title and symbol of instruction. Indicates usable CPUs. O : Usable : Usable with some CPUs or needs special operations for use. X : Unusable If the instruction is usable with all types of CPUs, it is indicated as follows. Applicable All CPUs Describes details of 2).
Page 69 4. INSTRUCTION FORMAT MELSEC-A REMARK Program display in list mode is as follows. M9036 DBIN K6X020 K10000 K4X010 Step No. Instruction Devices For the input procedure of the program, refer to the Operating Manual of respective peripheral device. 4 − 4...
Page 70: Sequence Instructions
5. SEQUENCE INSTRUCTIONS MELSEC-A 5. SEQUENCE INSTRUCTIONS Sequence instructions are used for relay control circuits, etc. and classified as follows. Classification Description Refer to: Contact instruction Operation start, series connection, parallel connection Connection Ladder block series connection, parallel connection, instruction operation result storage Bit device output, differential output, set, reset, output Output instruction...
Page 71: Contact Instructions
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.1 Contact Instructions Applicable All CPUs 5.1.1 Operation start, series connection, parallel connection (LD, LDI, AND, ANI, OR, ORI) Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *1: Index qualification can be used with AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only. Device number X001 X001...
Page 72 5. SEQUENCE INSTRUCTIONS MELSEC-A 2) Read: When AND or ANI is connected serially, a circuit of up to 24 stages can be displayed at one time. if a circuit has 25 or more stages, stages 1to 24 are displayed at one time. OR, ORI (1) OR is the parallel connection instruction of one contact A and ORI is the parallel connection instruction of one contact B.
Page 73 5. SEQUENCE INSTRUCTIONS MELSEC-A Program Examples LD , LD2 , AND , ANI , OR , ORI • Coding X003 X003 Y033 X004 X004 X005 Y033 X005 X005 X006 X005 Y034 Y034 X006 • Coding X003 X003 Y033 X004 X007 X004 X007 X005...
Page 74: Connection Instructions
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.2 Connection Instructions Applicable All CPUs 5.2.1 Ladder block series connection, parallel connection (ANB, ORB) Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Block A Block B Block A Block B For the parallel connection of one contact, use OR or ORI.
Page 75 5. SEQUENCE INSTRUCTIONS MELSEC-A (1) This instruction performs the OR operation of block A and block B, and uses it as an operation result. (2) ORB performs parallel connection of circuit blocks with two or more contacts. For parallel connection of circuit blocks which have only one contact, OR and ORI are used and ORB is not required.
Page 76 5. SEQUENCE INSTRUCTIONS MELSEC-A Program Examples When circuit blocks are serially connected consecutively, the coding of program is available in two types. However, proceed with the coding according to Coding example 1. X000 X002 X004 X006 X008 X001 X003 X005 X007 X009 •...
Page 77 5. SEQUENCE INSTRUCTIONS MELSEC-A When circuit blocks are parallelly connected consecutively, the coding of program is available in two types. However, proceed with the coding according to Coding example 1. X000 X001 X002 X003 X004 X005 X006 X007 • Coding example 1 •...
Page 78: Operation Result Push, Read, Pop (Mps, Mrd, Mpp)
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.2.2 Operation result push, read, pop (MPS, MRD, MPP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) When the ladder is dispiayed, MPS, MRD, and MPP are omitted. Functions (1) Stores the operation result (ON/OFF) immediately preceding the MPS instruction.
Page 79 5. SEQUENCE INSTRUCTIONS MELSEC-A (1) Reads the operation result stored by the MPS instruction, and resumes the operation with that operation result, starting at the next step. (2) Clears the operation result stored by the MPS instruction. POINT (1) When MPS, MRD, and MPP are used and when they are not used, the circuits differ as shown below.
Page 80 5. SEQUENCE INSTRUCTIONS MELSEC-A POINT (2) Set the numbers of used MPS and MPP instructions to the same. If the used numbers differ, the following occurs. 1) When the number of MPS instructions is larger than that of MPP instructions, the PC performs operation in the changed circuit. •...
Page 81 5. SEQUENCE INSTRUCTIONS MELSEC-A Program Examples MPS , MRD , (1) Program which uses MPS, MRD, and MPP. • Coding X01C X01C Y030 Y031 Y030 X01D Y032 Y031 X01D Y033 Y034 X01E Y032 Y035 Y036 Y033 Y034 Y037 X01E (10) Y038 Y035 Y036...
Page 82 5. SEQUENCE INSTRUCTIONS MELSEC-A (2) Printing example by use of MPS and MPP instructions. • Circuit printing X000 X001 X002 X003 X004 X005 X006 X007 X008 X009 X00A Y040 Y041 Y042 Y043 Y044 Y045 Y046 Y047 Y048 Y049 Y04A CIRCUIT END •...
Page 83: Output Instructions
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.3 Output Instructions Applicable All CPUs 5.3.1 Bit device, timer, counter output (OUT) Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Bit device Device Set Value Device Set value *1: Index qualification can be used AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only. *2: If extension timers or counters are used with the AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.3.
Page 84 5. SEQUENCE INSTRUCTIONS MELSEC-A POINTS (1) When F (annunciator) is turned ON, LED indicators and ERROR LEDs on the CPU module illuminate, and the number of annunciator which is turned ON is stored in special registers. For details, refer to the ACPU Programming Manual (Fundamentals).
Page 85 5. SEQUENCE INSTRUCTIONS MELSEC-A OUT (T) (1) When the operation result of instructions preceding the OUT instruction are on, the coil of timer turns on and counts up to the set value. When the timer times out (counted value set value), the contact is as indicated below. NO contact Continuity NC contact...
Page 86 5. SEQUENCE INSTRUCTIONS MELSEC-A (5) A negative number (-32768 to -1) cannot be used as a set value. When the set value is 0, the same processing as for 1 is performed. (6) For the counting process of counters, refer to the ACPU Programming Manual (Fundamentals).
Page 87 5. SEQUENCE INSTRUCTIONS MELSEC-A (4) Program which turns on Y30 after X0 turns on 10 times and which turns off Y30 when X1 turns on. • Coding X000 X000 Y030 Y030 X001 X001 RST C10 (5) Program which changes the set value of C10 to 10 when X0 turns on and to 20 when X1 turns on.
Page 88: Bit Device Set, Reset (Set,Rst)
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.3.2 Bit device set, reset (SET,RST) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *1: Index qualification can be used with AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only. SET input Setting data Device number to...
Page 89 5. SEQUENCE INSTRUCTIONS MELSEC-A (3) The functions of RST (D, W, R, A0, A1, Z, V) are the same as those of the following circuit. RST input RST input X010 X010 Device number Device number (D, W, R, A0, A1, Z, V) (D, W, R, A0, A1, Z, V) If the annunciator relay (F ) is turned ON/OFF, display contents of LED indicators...
Page 90 5. SEQUENCE INSTRUCTIONS MELSEC-A Program Examples SET , RST (1) Program which sets (turns on) Y8B when X8 turns on and which resets (turns off) Y8B when X9 turns on. X009 • Coding Y08B X009 X008 Y08B Y08B X008 Y08B X8 (SET input) X9 (RST input) (2) Program which sets the content of data register to 0.
Page 91 5. SEQUENCE INSTRUCTIONS MELSEC-A (3) Program which resets the 100ms retentive timer and counter. X004 K18000 T225 turns on after X4 has been T225 on for 30 minutes. T225 The number of ON times of T225 is counted. T225 When T225 has turned on, T225 is reset. Y055 When C23 has counted up, Y55 turnes on.
Page 92: Edge-Triggered Differential Output (Pls, Plf)
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.3.3 Edge-triggered differential output Applicable (PLS, PLF) All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *1: Index qualification can be used with AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only. PLS command PLS command Setting data...
Page 93 5. SEQUENCE INSTRUCTIONS MELSEC-A (2) If the instruction generating the pulse is switched on and the RUN key switch is moved from the RUN to STOP position and the RUN key switch is moved from the RUN to STOP position and then returned to the RUN position again, the PLS instruction is not executed.
Page 94 5. SEQUENCE INSTRUCTIONS MELSEC-A POINT If a PLS or PLF instruction is caused to jump by a CJ instruction, if the sub-routine program executed by a PLS/PLF command was not called by a CALL instruction, the device specified by (D) will go On for 1 scan or longer, so exercise caution.
Page 95: Bit Device Output Reverse (Chk)
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.3.4 Bit device output reverse (CHK) AnU, A2AS A2USH-S1 A1FX A2USH board A0J2H A52G boad Applicable AnSH QCPU-A (A Mode) Remark * Valid only when the input/output control method is refresh method. The CHK instruction varies in function with I/0 control mode as shown below. I/O control mode Refresh mode Direct mode...
Page 96 5. SEQUENCE INSTRUCTIONS MELSEC-A Functions (1) Reverses the output status of the device, (D1), on the leading edge of the output reverse command. (2) Though (D2) is a dummy data, specify any device number indicated with the mark for it. If a bit device is specified for (D2) , specify the digit with K1 to K4. Specify any value since this digit specification value is a dummy data.
Page 97: Shift Instructions
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.4 Shift Instructions Applicable All CPUs 5.4.1 Bit device shift (SFT, SFTP) Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *1: Index qualification can be used with AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only. SFT instruction Setting data Device number to be...
Page 98 5. SEQUENCE INSTRUCTIONS MELSEC-A Program Example (1) Program which shifts the Y57 to 5B when X8 turns on. X008 Y05B Y05A When X8 turns on, shift is executed. (Perform programming in order of larger device numbers.) Y059 Y058 X007 When X7 turns on, Y57 is turned on.
Page 99: Master Control Instructions
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.5 Master Control Instructions Applicable All CPUs 5.5.1 Master control set, reset (MC, MCR) Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *1: Index qualification can be used with AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only. ON/OFF command for MC (D) ←...
Page 100 5. SEQUENCE INSTRUCTIONS MELSEC-A Functions (1) MC is master control start instruction. When the ON/OFF command for the MC is on, operation results from MC to MCR remain unchanged. (2) Scanning between the MC and MCR instructions is executed even when the ON/OFF command for the MC instruction is OFF.
Page 101 5. SEQUENCE INSTRUCTIONS MELSEC-A The MC instructions can be used by nesting. Range of each MC instruction is identified by a nesting number. Nesting numbers are used in the range of N0 to N7. Using nesting, circuits which sequentially restrict execution conditions of a program can be made.
Page 102 5. SEQUENCE INSTRUCTIONS MELSEC-A (2) If the MCR instructions gather at one place of nesting, use the lowest nesting number (N) once to end all MCs. X001 X001 MC N0 MC N0 X002 X002 MC N1 MC N1 X003 X003 MC N2 MC N2 MCR N2...
Page 103: Termination Instructions
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.6 Termination Instructions Applicable All CPUs 5.6.1 Main routine program termination (FEND) Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) FEND Functions (1) Terminates the main routine program. (2) When the FEND instruction is executed, the PC returns to step 0 after the processing (such as timer/counter processing and self-diagnostic check) after the execution of END instruction, and resumes operation from step 0.
Page 104 5. SEQUENCE INSTRUCTIONS MELSEC-A Program Example FEND (1) Program which uses the CJ instruction. X000 Y020 X00B When XB is on, jump is made to label P23 and execution is performed from the next step to P23. X013 Y030 Executed when XB is off. X014 Y031 Indicates the end of sequence program when XB...
Page 105: Sequence Program Termination (End)
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.6.2 Sequence program termination (END) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) When the ladder is displayed, END is omitted. Functions (1) This instruction indicates the end of program. At this step, the scan returns to step 0.
Page 106 5. SEQUENCE INSTRUCTIONS MELSEC-A (4) Use the END and FEND instructions in the main routine program, subroutine program, interrupt program, and subsequence program as shown below. Main routine program FEND (FEND instruction is always required.) Subroutine program Main sequence program area Interrupt program (END instruction is always required.)
Page 107: Other Instructions
5. SEQUENCE INSTRUCTIONS MELSEC-A 5.7 Other Instructions Applicable All CPUs 5.7.1 Sequence program stop (STOP) Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Stop input STOP Functions (1) When the stop input turns on, resets the outputs Y and stops the operation of PC.
Page 108 5. SEQUENCE INSTRUCTIONS MELSEC-A Program Examples STOP (1) Program which stops the PC when X8 turns on. X008 STOP When X8 turns on, PC is stopped. X00A Y013 Sequence program X00B Y023 • Coding X008 STOP X00A Y013 X00B Y023 5 −...
Page 109: No Operation (Nop, Noplf)
5. SEQUENCE INSTRUCTIONS MELSEC-A Applicable All CPUs 5.7.2 No operation (NOP, NOPLF) The NOPLF instruction can be used with the GPP of which software is SW4GP-GPPA or SW01X-GPPAE. Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) When the ladder is displayed, NOP is omitted.
Page 110 5. SEQUENCE INSTRUCTIONS MELSEC-A 2) For printing instuction lists • Page is changed after NOPLF is printed. 3) For the GPP printer output, refer to the Operating Manual for peripheral devices. Program Examples (1) Program which stops the PC when X8 turns on. Before change X008 Y097 Y096...
Page 111 5. SEQUENCE INSTRUCTIONS MELSEC-A Before change X000 Coding Y016 X056 Y066 Changed to NOP. Changed to LD T3. After change Coding 5 − 42...
Page 112 5. SEQUENCE INSTRUCTIONS MELSEC-A NOPLF • Cording Not displayed in the ladder mode. X000 X000 NOPLF NOPLF NOPLF NOPLF X001 X001 Y040 Y040 • A printout example of ladder diagrams X000 The NOPLF instruction in the ladder block is ignored. NOPLF (Not printed by ladder printing.) NOPLF...
Page 113: Basic Instructions
6. BASIC INSTRUCTIONS MELSEC-A 6. BASIC INSTRUCTIONS The basic instructions are instructions which are capable of handing numeric data expressed in 16 bits and 32 bits, and are classified into the following instructions. Classification of Basic Instructions Description Ref. Page Comparison operation instruction Comparison such as =, >, and <...
Page 114: Comparison Operation Instructions
6. BASIC INSTRUCTIONS MELSEC-A 6.1 Comparison Operation Instructions (1) The comparison operation instructions make numerical magnitude comparisons (such as =, >, and <) between two pieces of data. They are handled as a contact, and turn on when their preceding condition holds. (2) The application of comparison operation instruction is the same as that of the contact instruction for the corresponding sequence instruction as indicated below:...
Page 115 6. BASIC INSTRUCTIONS MELSEC-A CAUTION (1) The comparison instructions make the comparison, regarding the specified data as a BIN value. For this reason, in the case of comparison made in BCD value or hexadecimal, when a numeric value (8 to F) having 1 at the highest bit (B15 in a 16-bit instruction or B31 in a 32-bit instruction) is specifies, the comparison is made with the numeric value regarded as the negative of the BIN value.
Page 116: 16-Bit Data Comparison
6. BASIC INSTRUCTIONS MELSEC-A 6.1.1 16-bit data comparison (=, <>, >, <=, <, >=) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) Indicates the instruction symbol. (S1) (S2) =, <>,> <=, <, >= Setting data (S1)
Page 117 6. BASIC INSTRUCTIONS MELSEC-A REMARK The number of steps is seven in the following cases: • Index qualification has been performed. • The digit specification of bit device is not K4. • The head number of bit device is not a multiple of 8. A multiple of 16 when the A3H, A3M, or A ACPU is used.
Page 118: 32-Bit Data Comparison (D=, D<>, D>, D<=, D<,D>=)
6. BASIC INSTRUCTIONS MELSEC-A 6.1.2 32-bit data comparison (D=, D<>, D>, D<=, D<,D>=) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) Instruction symbol (S1) (S2) D=, D<>,D> D<=, D<, D>= Setting data (S1) (S2)
Page 119 6. BASIC INSTRUCTIONS MELSEC-A Program Examples (1) Program which compares the data of X0 to 1F and the data of D3 and D4. • Coding LDD= K8X000 D3 Y033 X000 Y033 D<> (2) Program which compares the BCD value 18000 and the data of D3 and D4. •...
Page 120: Arithmetic Operation Instructions
6. BASIC INSTRUCTIONS MELSEC-A 6.2 Arithmetic Operation Instructions The arithmetic operation instructions are instructions which perform the addition, subtraction, multiplication, and division of two BIN data or BCD data. The arithmetic operation instructions are available in the following 56 types. Classification Instruction Instruction...
Page 121 6. BASIC INSTRUCTIONS MELSEC-A Arithmetic operation with BIN (Binary) • If the operation result of an addition instruction exceeds 32767 (2147483647 in the case of a 32-bit instruction), the result becomes a negative value. • If the operation result of a subtraction instruction is less than - 32768 (-2147483648 in the case of a 32-bit instruction), the result becomes a positive value.
Page 122: Bin 16-Bit Addition, Subtraction (+, +P, -, -P)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.1 BIN 16-bit addition, subtraction (+, +P, -, -P) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) (D1) Addition/subtraction commands Indicates the instruction symbol. +, - Setting data Addend/subtrahend or head device number stor-...
Page 123 6. BASIC INSTRUCTIONS MELSEC-A (3) At (S), (S1), (S2) and (D), -32768 to 32767 (BIN 16 bits) can be specified. (4) The judgment of whether the data of (S), (S1), (S2) and (D) are positive or negative is made at the highest bit (b15). 0 ⋅⋅⋅⋅⋅⋅...
Page 124 6. BASIC INSTRUCTIONS MELSEC-A Execution Conditions Addition/subtraction command Executed Executed per scan per scan Executed Executed only once only once Program Examples Program which adds the content of A0 to the content of D3 and outputs the result to Y38 to 3F when X5 turns on. •...
Page 125: Bin 32-Bit Addition, Subtraction (D+, D+P, D-, D-P)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.2 BIN 32-bit addition, subtraction (D+, D+P, D-, D-P) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) (D1) Indicates the instruction symbol. Addition/subtraction commands D+, D- Setting data Addend/subtrahend or head device number stor-...
Page 126 6. BASIC INSTRUCTIONS MELSEC-A (3) At (S), (S1), (S2) and (D), -2147483648 to 2147483647 (BIN 32 bits) can be specified. (4) The judgement of whether the datas of (S), (S1), (S2) and (D) are positive or negative is made at the highest bit (b31). 0…….
Page 127 6. BASIC INSTRUCTIONS MELSEC-A Execution Conditions Addition/subtraction command Executed Executed per scan per scan Executed Executed only once only once Program Examples Program which adds the 28-bit data of X10 to 2B and the date of D9 and 10, and outputs the result to Y30 to 4B when X0 turns on.
Page 128: Bin 16-Bit Multiplication, Division (*, *P, /, /P)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.3 BIN 16-bit multiplication, division (*, *P, /, /P) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) Indicates the instruction symbol. Multiplication/division commands ∗, / Setting data (S1) (S2) Multiplicand/dividend or...
Page 129 6. BASIC INSTRUCTIONS MELSEC-A (1) Performs the division of BIN data specified at (S1) and the BIN data specified at (S2), and stores the result into the device specified at (D). (2) In regards to the operation result, the quotient and remainder are stored by use of 32 bits in the case of word device, and only the quotient is stored by use of 16 bits in the case of bit device.
Page 130 6. BASIC INSTRUCTIONS MELSEC-A Program Examples (1) Program which stores the multiplication result of 5678 and 1234 in BIN to D3 and 4 when X5 turns on. • Coding X005 X005 5678 1234 K5678 K1234 (2) Program which outputs the multiplication result of the BIN data of X8 to F and the BIN data of X10 to 1B to Y30 to 3F.
Page 131: Bin 32-Bit Multiplication, Division (D*, D*P, D/, D/P)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.4 BIN 32-bit multiplication, division (D*, D*P, D/, D/P) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) Indicates the instruction symbol. Multiplication/division commands D*, D/ Setting data (S1) (S2) Multiplicand/dividend or...
Page 132 6. BASIC INSTRUCTIONS MELSEC-A (3) At (S1) and (S2), -2147483648 to 2147483647 (BIN 32 bits) can be specified. (7) The judgment of whether the data of (S1) and (S2) are positive or negative is made at the highest bit (b31) and that of (D), at (b63). (1) Performs the division of BIN data specified at (S1) and the BIN data specified at (S2), and stores the division result into the device specified at (D).
Page 133 6. BASIC INSTRUCTIONS MELSEC-A Program Examples Program which stores the multiplication result of the BIN data of D7 and D8 and the BIN data of D18 and D19 to D1 to D4 when X5 turns on. X005 • Coding X005 Program which outputs a value, obtained by multiplying the data of X8 to F by 3.14, to Y30 to 3F when X3 turns on.
Page 134: Bcd 4-Digit Addition, Subtraction (B+, B+P, B-, B-P)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.5 BCD 4-digit addition, subtraction (B+, B+P, B-, B-P) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) (D1) Indicates the instruction symbol. Addition/subtraction commands B+, B- Setting data Addend/subtrahend or head device number stor-...
Page 135 6. BASIC INSTRUCTIONS MELSEC-A (1) Performs the subtraction of BCD data specified at (D) and the BCD data specifi-ed at (S), and stores the subtraction result into the device specified at (D). Digit higher than the specified digit is regarded as 0. (2) Performs the subtraction of BCD data specified at (S2) and the BCD data speci-fied at (S1), and stores the subtraction result into the device specified at (D1).
Page 136 6. BASIC INSTRUCTIONS MELSEC-A Program Examples Program which performs the addition of BCD data 5678 and 1234, and stores the result to D993, and at the same time outputs it to Y30 to 3F. M9036 5678 D993 5678 is stored into D993 in BCD 1234 D993 BCD data 1234 and D993 are added and the...
Page 137: Bcd 8-Digit Addition, Subtraction (Db+, Db+P, Db-, Db-P)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.6 BCD 8-digit addition, subtraction (DB+, DB+P, DB-, DB-P) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) (D1) Indicates the instruction symbol. Addition/subtraction commands DB+, DB- Setting data Addend/subtrahend or head device number stor-...
Page 138 6. BASIC INSTRUCTIONS MELSEC-A (3) At (S), (S1), (S2) and D, 0 to 99999999 (BCD 8 digits) can be specified. (4) Even if the addition result exceeds 99999999, the carry flag does not turn on and the carry digit is ignored. (1) Subtracts the BCD data specified at (S) from the BCD data specified at (D), and stores the subtraction result into the device specified at (D).
Page 139 6. BASIC INSTRUCTIONS MELSEC-A Program Examples Program which performs the addition of BCD data 98765400 and 123456, and stores the result to D888 and D887, and at the same time, outputs it to Y30 to 4F. M9036 DMOV 98765400 D887 98765400 is stored into D888 and D887 in BCD.
Page 140: Bcd 4-Digit Multiplication, Division (B*, B*P, B/, B/P)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.7 BCD 4-digit multiplication, division (B*, B*P, B/, B/P) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) Multiplication/division commands Indicates the instruction symbol. B∗, B/ Setting data Multiplicand/dividend or (S1) head device number stor-...
Page 141 6. BASIC INSTRUCTIONS MELSEC-A Execution Conditions Multiplication/division commands Executed Executed per scan per scan Executed Executed only once only once Operation Errors In the following cases, operation error occurs and the error flag turns on. • A value other than 0 to 9 exists in any digit of (S1), (S2). •...
Page 142 6. BASIC INSTRUCTIONS MELSEC-A Program which performs the division of BCD data 5678 and 1234, and stores the result to D502 and 503, and at the same time, outputs the quotient to Y30 to 3F. M9036 Division of BCD data 5678 and 1234 is performed 5678 1234 D502...
Page 143: Bcd 8-Digit Multiplication, Division (Db*, Db*P, Db/, Db/P)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.8 BCD 8-digit multiplication, division (DB*, DB*P, DB/, DB/P) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) Multiplication/division commands Indicates the instruction symbol. DB∗, DB/ Setting data Multiplicand/dividend or (S1) head device number stor-...
Page 144 6. BASIC INSTRUCTIONS MELSEC-A (1) Performs division of the BCD data specified at (S1) and the BCD data specified at (S2), and stores the division result into the device specified at (D). Digit higher than the specified digit is regarded as 0. (2) In regards to the operation result, the quotient and remainder are stored by use of 64 bits.
Page 145 6. BASIC INSTRUCTIONS MELSEC-A Program Examples Program which performs multiplication of the BCD data 68347125 and 573682, and stores the result to D505 to 502, and at the same time, outputs the upper 8 digits to Y30 to 4F. • Coding M9036 M9036 68347125...
Page 146: 16-Bit Bin Data Increment, Decrement (Inc, Incp, Dec, Decp)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.9 16-bit BIN data increment, decrement (INC, INCP, DEC, DECP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) INC, DEC commands Indicates the instruction symbol. INC, DEC Setting data Head device number for INC (+1), DEC (-1) Functions...
Page 147 6. BASIC INSTRUCTIONS MELSEC-A Program Examples Program which outputs the present value of counters C0 to C20 in BCD to Y30 to 3F each time X8 turns on. (When the present value < 9999) X008 The present value of C(0+Z) is output to the Y30 to 3F in BCD. Y030 Z + 1 is executed RST Z...
Page 148: 32-Bit Bin Data Increment, Decrement (Dinc, Dincp, Ddec, Ddecp)
6. BASIC INSTRUCTIONS MELSEC-A 6.2.10 32-bit BIN data increment, decrement (DINC, DINCP, DDEC, DDECP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) DINC, DDEC commands Indicates the instruction symbol. DINC, DDEC Setting data Head device number for DINC (+1), DDEC(-1) Functions...
Page 149 6. BASIC INSTRUCTIONS MELSEC-A Program Examples DINC (1) Program which adds 1 to the data of D0 and 1when X0 turns on. • Coding X000 X000 DINC DINCP (2) Program which adds 1 to the data of X10 to 27 and stores the result to D3 and 4 when X0 turns on.
Page 150: Bcd ↔ Bin Conversion Instructions
6. BASIC INSTRUCTIONS MELSEC-A 6.3 BCD ↔ BIN Conversion Instructions The BCD ↔ BIN conversion instructions are instructions which convert BCD data to BIN data and BCD data. Instruction Instruction Classification Ref. Page Classification Ref. Page Symbol symbol 6-39 6-42 BCDP 6-39 BINP...
Page 151: Bin Data → Bcd 4-, 8-Digit Conversion (Bcd, Bcdp, Dbcd, Dbcdp)
6. BASIC INSTRUCTIONS MELSEC-A 6.3.1 BIN data → BCD 4-, 8-digit conversion Applicable All CPUs (BCD, BCDP, DBCD, DBCDP) Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) DBCD BCD conversion commands Indicates the instruction symbol. BCD, DBCD Setting data BIN data or head number...
Page 152 6. BASIC INSTRUCTIONS MELSEC-A DBCD Converts BIN data (0 to 99999999) of the device specified at S into BCD and transfers the result to the device specified at D. (S) + 1 (Upper 16 bits) (S) (Lower 16 bits) (S) side BIN 99999999 BCD conversion Be sure to set to 0 (Upper 5 bits)
Page 153 6. BASIC INSTRUCTIONS MELSEC-A Program Examples Program which outputs the present value of C4 from the Y20 to 2F to the BCD indicator. PC output unit Output power source 7-element indicator • Coding M9036 M9036 Y202 BCDP K4Y020 DBCD Program which outputs the 32-bit data of D0 and D1 to Y40 to Y67. PC output unit Input power source...
Page 154: Bcd 4-, 8-Digit → Bin Data Conversion (Bin, Binp, Dbin, Dbinp)
6. BASIC INSTRUCTIONS MELSEC-A 6.3.2 BCD 4-, 8-digit → BIN data conversion (BIN, BINP, DBIN, DBINP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) DBIN BIN conversion commands Indicates the instruction symbol. BIN, DBIN Setting data BCD data or head number...
Page 155 6. BASIC INSTRUCTIONS MELSEC-A DBIN Converts BCD data (0 to 99999999) of device specified at (S) into BIN and transfers the result to the device specified at (D). (S) + 1 (S) side BCD 99999999 BIN conversion (D) + 1 (D) side BIN 99999999 Always set to 0.
Page 156 6. BASIC INSTRUCTIONS MELSEC-A Program Examples Program which converts the BCD data of X10 to 1B into BIN and stores the result into D8 when X8 turns on. Digital switch Can be used for others. Input power source PC input unit X008 X010 •...
Page 157 6. BASIC INSTRUCTIONS MELSEC-A DBIN Program which converts the BCD data of X10 to 37 into BIN and stores the result into D0 and 1. (The addition of BCD data X20 to X37 converted into BIN and BCD data X10 to X1F converted into BIN.) BCD Digital switch Input power...
Page 158: Data Transfer Instructions
6. BASIC INSTRUCTIONS MELSEC-A 6.4 Data Transfer Instructions The data transfer instructions are instructions which perform data transfer, interchanging data, the negative (reverse) data transfer, etc. Classification Instruction Symbol Ref. Page 6-47 MOVP 6-47 Transfer DMOV 6-47 DMOVP 6-47 6-49 CMLP 6-49 Negative transfer...
Page 159: 32-Bit Data Transfer (Mov, Movp, Dmov, Dmovp)
6. BASIC INSTRUCTIONS MELSEC-A 6.4.1 16-, 32-bit data transfer (MOV, MOVP, DMOV, DMOVP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) DMOV Transfer commands Indicates the instruction symbol. MOV, DMOV Setting data Data of transfer source or head number of device which stores data.
Page 160 6. BASIC INSTRUCTIONS MELSEC-A Execution Conditions Transfer command Executed Executed per scan per scan Executed Executed only once only once Programs Examples (1) Program which stores the data of inputs X0 to B into D8. • Coding X9036 P K3 MOV x000 M9036 MOVP...
Page 161: 32-Bit Data Negation Transfer (Cml, Cmlp, Dcml, Dcmlp)
6. BASIC INSTRUCTIONS MELSEC-A 6.4.2 16-, 32-bit data negation transfer (CML, CMLP, DCML, DCMLP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) DCML Indicates the instruction symbol. Negative transfer commands CML, DCML Setting data Data to be reversed or head number of device...
Page 162 6. BASIC INSTRUCTIONS MELSEC-A Execution Conditions Negative transfer command Executed Executed per scan per scan Executed Executed only once only once Program Examples (1) Program which reverses the data of X0 to 7 and transfers the result to D0. • Coding M9038 M9038 X000...
Page 163 6. BASIC INSTRUCTIONS MELSEC-A DCML (1) Program which reverses the data of X0 to 1F and transfers the result to D0 and 1. • Coding M9038 M9038 DCML X000 DCML K8X000 D0 The number of bits of (S) < The number of bits of (D): These bits are all regarded 0.
Page 164: 16-Bit Data Block Transfer (Bmov, Bmovp, Fmov, Fmovp)
6. BASIC INSTRUCTIONS MELSEC-A 6.4.3 16-bit data block transfer (BMOV, BMOVP, FMOV, FMOVP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) BMOV FMOV Indicates the instruction symbol. Transfer commands BMOV, FMOV Setting data Head number of device which stores data to be transferred...
Page 165 6. BASIC INSTRUCTIONS MELSEC-A FMOV Transfers the content of device specified at (S) in blocks to "n" points which begin with the device specified at (D). Execution Conditions Transfer commands Executed Executed per scan per scan Executed Executed only once only once Operation Error In the following case, operation error occurs and the error flag turns on.
Page 166 6. BASIC INSTRUCTIONS MELSEC-A Program Examples BMOV (1) Program which output the data of the lower 4 bits of D66 to 69 to the Y30 to 3F in units of 4 points. • Coding M9038 M9038 BMOV Y030 BMOV K1Y030 Before execution After execution (Transfer source)
Page 167 6. BASIC INSTRUCTIONS MELSEC-A FMOV (1) Program which outputs the data of the lower 4 bits of D0 to Y10 to 23 in units of 4 points when XA turn on. Ignored Transfer • Coding X00A X00A FMOV Y010 FMOVP D0 K1Y010 (2) Program which outputs the data of X20 to X23 to D100 to D103 when XA is turned on.
Page 168: 32-Bit Data Exchange (Xch, Xchp, Dxch, Dxchp)
6. BASIC INSTRUCTIONS MELSEC-A 6.4.4 16-, 32-bit data exchange (XCH, XCHP, DXCH, DXCHP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (D1) (D2) (D1) DXCH (D2) Interchange commands Indicates the instruction symbol. (D1) (D2) XCH, DXCH...
Page 169 6. BASIC INSTRUCTIONS MELSEC-A Execution Conditions Interchange command Executed Executed per scan per scan Executed Executed only once only once Program Examples (1) Program which interchanges the present value of T0 and the content of D0 when X8 turns on. •...
Page 170: Program Branch Instructions
6. BASIC INSTRUCTIONS MELSEC-A 6.5 Program Branch Instructions Applicable All CPUs 6.5.1 Conditional jump, unconditional jump (CJ, SCJ, JMP) Available Device Bit device Word (16-bit) device Constant Pointer Level (M9010, M9012 M9011) Jump commands Setting data Pointer number of jump Jump destination (P0 to P255) destination...
Page 171 6. BASIC INSTRUCTIONS MELSEC-A (1) Executes the program of specified pointer number unconditionally. Consider the following when the jump instructions are used. (2) Even if the timer, of which coil is on, is jumped by the CJ, SCJ, or JMP instruction after the coil of timer is turned on, the timer continues counting.
Page 172 6. BASIC INSTRUCTIONS MELSEC-A Operation Errors In the following cases, operation error occurs and the PC stops its operation. • When there are mult. contacts of the same labels, a jump has been made to that label by the CJ, SCJ, or JMP instruction. •...
Page 173 6. BASIC INSTRUCTIONS MELSEC-A (2) Program which causes a jump during the next scan to P3 when XC turns on. • Coding X00C X00C X030 X030 Y06F Y06F X041 X041 Y07E Y07E (1) Program which causes a jump to the END instruction when X9 turns on. •...
Page 174: Subroutine Call, Return (Call, Callp, Ret)
6. BASIC INSTRUCTIONS MELSEC-A 6.5.2 Subroutine call, return (CALL, CALLP, RET) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Subroutine execution commands CALL Call of subroutine Setting data program Head pointer number of CALLP subroutine program (P0 to Head pointer number...
Page 175 6. BASIC INSTRUCTIONS MELSEC-A Execution The execution conditions of CALL and CALLP are a shown below. Conditions Subroutine execution command Executed CALL Executed per scan per scan Executed CALLP only once Executed only once When a program uses the PLS and PLF instructions in the subroutine, and when the ON/OFF time of a subroutine execution designation signal is set shorter than the scan time, the device designated with (D) of the subroutine PLS and PLF instructions may sometimes remain turned ON more than 1 scan.
Page 176 6. BASIC INSTRUCTIONS MELSEC-A Program Example CALL , RET (1) Program which executes the subroutine program when X1 changes from off to X008 • Coding Y011 X008 X001 Y011 CALL X001 X009 CALLP Y013 X009 Y013 FEND FEND X00A X000 Y033 Y033 Y034...
Page 177: Interrupt Enable, Disable, Return (Ei, Di, Iret)
6. BASIC INSTRUCTIONS MELSEC-A 6.5.3 Interrupt enable, disable, return AnU, A2AS A2USH-S1 A2USH board A1FX A0J2H (EI, DI, IRET) Applicable A52G board AnSH QCPU-A (A Mode) Remark * EI and DI instructions are valid only when special relay M9053 is OFF. The EI and DI instructions used with the AnN, AnS, AnSH, A1FX, A0J2H, A73 and A3N vary in function with status of special relay M9053, as mentioned below.
Page 178 6. BASIC INSTRUCTIONS MELSEC-A (1) Enables the interrupt program. Sequence program Any interrupt signal occuring between DI and EI instructions, is disabled Sequence program until the processing between the DI and EI instructions is completed after which the interrupt program is run. FEND Interrupt program IRET...
Page 179 6. BASIC INSTRUCTIONS MELSEC-A Operation Error If the IRET instruction is executed prior to the run of interrupt program, the PC stops its operation. Sequence program When IRET instruction is executed, IRET PC stops operation. FEND Interrupt program IRET Program Example EI , DI Disable/enable program of the run of interrupt program by DI and EI.
Page 180: Microcomputer Program Call (Sub, Subp)
6. BASIC INSTRUCTIONS MELSEC-A 6.5.4 Microcomputer program call AnU, A2AS A2USH-S1 A1FX A2USH board A0J2H (SUB, SUBP) Applicable A52G board AnSH QCPU-A (A Mode) Remark The SUB instruction of the AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board becomes the 16-bit constant setting instruction in the extension application instructions.
Page 181 6. BASIC INSTRUCTIONS MELSEC-A (4) In the microcomputer program area, multiple microcomputer programs can be created. Head of microcomputer program X010 0500 Microcomputer 500H X011 program 0930 Microcomputer 930H program (5) For the details of microcomputer program, see Section 8. Execution The execution conditions of SUB and SUBP instructions are as shown below.
Page 182: Program Switching Instructions
6. BASIC INSTRUCTIONS MELSEC-A AnU, A2AS 6.6 Program Switching Instructions A2USH-S1 A1FX A2USH board A0J2H A52G boad Applicable AnSH QCPU-A 6.6.1 Main ↔ subprogram switching (CHG) (A Mode) *1: A3N only *3: A3A only Remark *2: A3 only *4: A3U, A4U and Q06H only Available Device Bit device Word (16-bit) device...
Page 183 6. BASIC INSTRUCTIONS MELSEC-A (2) For further information on functions and applications, refer to the use of subprograms given in the ACPU Programming Manual (Fundamentals). POINTS (1) A4U's CHG instruction is used to switch subsequence programs 1, 2, and 3 which are set in the main sequence program. When up to subsequence program 2 has been set, programs are switched as the main sequence program →...
Page 184 6. BASIC INSTRUCTIONS MELSEC-A (2) When the A3N, A73, A3V and A3N board are used, the CHG instruction is only executed on the leading edge of its input condition. Since M9050 is not provided, execution contents of the CHG instruction are always same. The following program is written before END or FEND of the main and subsequence programs.
Page 185 6. BASIC INSTRUCTIONS MELSEC-A Execution of PLS Instruction Used with CHG Instruction (1) When the A3 is used, execution contents of the PLS instruction change with status of M9050 when other input conditions are same. Status of M9050 The following program is written at step 0 of the main and subsequence programs. Input condition Ladder example X000...
Page 186 6. BASIC INSTRUCTIONS MELSEC-A (3) When the A3H, A3M, A3A, A3U, A4U and Q06H are used, the CHG instruction is executed repeatedly while its input condition is on. The following program is written before END or FEND of the main and subsequence programs. Input condition Ladder example X000...
Page 187 6. BASIC INSTRUCTIONS MELSEC-A Execution of P Instruction Used with CHG Instruction (1) When the A3 is used, execution contents of the PLS instruction change with status of M9050 when other input conditions are same. Status of M9050 The following program is written at step 0 of the main and subsequence programs. Ladder example X000 1 scan...
Page 188 6. BASIC INSTRUCTIONS MELSEC-A (3) When the A3H, A3M, A3A, A3U, A4U and Q06H are used, the CHG instruction is executed repeatedly while its input condition is on. The following program is written at step 0 of the main and subsequence programs. X000 Ladder example 1scan...
Page 189 6. BASIC INSTRUCTIONS MELSEC-A Counting of Counter Used with CHG Instruction (1) When the A3 is used, execution contents of the counter change with status of M9050 when other input conditions are same. Status of M9050 The following program is written at step 0 of the main and subsequence programs. X000 Ladder example 1 scan...
Page 190 6. BASIC INSTRUCTIONS MELSEC-A (3) When the A3H, A3M, A3A, A3U, A4U and Q06H are used, execution contents are always same. The following program is written at step 0 of the main and subsequence programs. X000 Ladder example 1 scan CHG instruction execution Main sequence program run...
Page 191 6. BASIC INSTRUCTIONS MELSEC-A Timing of Timer Used with CHG Instruction Each of the CPUs with which the CHG instruction can be used has two timer set value storage areas; one for the main sequence program and the other for the subsequence program.
Page 192 6. BASIC INSTRUCTIONS MELSEC-A Execution of OUT Instruction Used with CHG Instruction When the CPUs with which the CHG instruction can be used are used, the coil switched on/off in the main (sub) sequence program remains unchanged during sub (main) sequence program run even if its input condition changes. The following program is written after the main sequence program and the same coil is not used in the subsequence program.
Page 193 6. BASIC INSTRUCTIONS MELSEC-A Program Examples The following programs are used with the A3CPU and other types of CPUs to output pulses in accordance with the input condition of the PLS instruction while alternately running the main and subprograms. (1) For A3CPU It is necessary to compare the operation result of a scan with that of the previous scan to allow correct output of the PLS instruction.
Page 194 6. BASIC INSTRUCTIONS MELSEC-A (3) For A3H, A3M, A3A, A3U, A4U and Q06H program Always on Always on M9036 M9051 M9057 M9036 M9051 M9056 FEND FEND Main sequence program Subsequence program CAUTION When modifying a subprogram during main program run or vice versa, M9051, M9056 and M9057 contacts should be used to disable the CHG instruction so that the CHG instruction may not switch the currently running program to the program currently being corrected.
Page 195: Link Refresh Instructions
6. BASIC INSTRUCTIONS MELSEC-A 6.7 Link Refresh Instructions AnU, A2AS A2USH-S1 A1FX A2USH board A0J2H A52G board Applicable AnSH QCPU-A 6.7.1 Link refresh (COM) (A Mode) Remark * Execution is not possible while an interrupt program is being run. Available Device Bit device Word (16-bit) device Constant...
Page 196 6. BASIC INSTRUCTIONS MELSEC-A Execution (1) Data communication using the COM instruction Conditions 1) Example without using the COM instruction Master station program Data communication Local station program Remote I/O station I/O refresh 2) Example using the COM instruction Master station program Data communication Local station program Remote I/O station...
Page 197: Link Refresh Enable, Disable (Ei, Di)
6. BASIC INSTRUCTIONS MELSEC-A 6.7.2 Link refresh enable, disable (EI, DI) AnU, A2AS A2USH-S1 A1FX A2USH board A0J2H A52G board Applicable AnSH QCPU-A (A Mode) Remark * Valid only when special relay M9053 is OFF. The EI/DI instructions change in function depending on the status of special relay M9053, as follows.
Page 198 6. BASIC INSTRUCTIONS MELSEC-A Execution (1) EI/DI instructions are not used Conditions Sequence Sequence Sequence processing processing processing (2) EI instruction is used Sequence Sequence Sequence processing processing processing (3) EI/DI instructions are used Sequence Sequence Sequence *: • indicates that link processing processing processing...
Page 199 6. BASIC INSTRUCTIONS MELSEC-A Program Example EI , The following program allows the interrupt program to be called at any time and link refresh to be disabled until the EI instruction is executed before the FEND instruction is executed. SET M9053 RST M9053 processing RST M9053...
Page 200: Partial Refresh (Seg)
6. BASIC INSTRUCTIONS MELSEC-A 6.7.3 Partial refresh (SEG) AnU, A2AS A2USH-S1 A1FX A2USH board A0J2H Applicable A52G board AnSH QCPU-A (A Mode) Remark * Valid only when special relay M9052 is OFF. The SEG instruction changes in function depending on the status of special relay M9052, as follows.
Page 201 6. BASIC INSTRUCTIONS MELSEC-A POINTS (1) When the A2C is used, pulse signals cannot be output during 1 scan due to data communication with I/O modules though partial refresh of output (Y) is done with the SEG instruction. For details, refer to the A2CCPU User's Manual.
Page 202 6. BASIC INSTRUCTIONS MELSEC-A (4) Partial refresh processing is still performed if the SEG instruction is executed with the CPU set in X/Y direct mode, but in this case, input (X)/output (Y) ON/OFF status does not change. (5) Setting B0 (0 point) refreshes all devices in the unit, beginning with the head device number specified.
Page 203: Application Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7. APPLICATION INSTRUCTIONS Application instructions are used when special processing is required. They are classified as follows: Classification of Application Instructions Description Ref. Page Logical operation such as logical add and logical Logical operation instruction product Rotation instruction Rotation of specified data 7-22...
Page 204: Logical Operation Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.1 Logical Operation Instructions (1) The logical operation instructions are instructions which perform the logical operations such as logical add and logical product. (2) The logical operation instructions are available in the following 26 types. Instruction Instruction Instruction Classification...
Page 205: 32-Bit Data Logical Product (Wand, Wandp, Dand, Dandp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.1.1 16-, 32-bit data logical product (WAND, WANDP, DAND, DANDP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) WAND (S1) (S2) (D1) DAND Operation commands Indicates the instruction symbol. WAND, DAND Setting data Data for which logical...
Page 206 7. APPLICATION INSTRUCTIONS MELSEC-A (2) Performs the logical product of the 16-bit data of device specified at (S1) and the 16-bit data of device specified at (S2) per bit, and stores the result into the device specified at (D1). 16 bits Before execution WAND After execution...
Page 207 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples WAND (1) Program which masks the digit of tens (the second digit from the right), among the BCD four digits of D10, and sets it to 0 when XA turns on. (D10) = 1234 → 1204 •...
Page 208 7. APPLICATION INSTRUCTIONS MELSEC-A (3) Program which performs logical product of the data of X10 to 1B and the data of D33, and sends the result to the Y30 to 3B when XA turns on. • Coding X00A X00A WAND X010 Y030 WANDP K3X010 D33...
Page 209 7. APPLICATION INSTRUCTIONS MELSEC-A (2) Program which performs logical product of the 32-bit data of D0 and 1 and the 32-bit data of D108 and 109, and sends the result to the Y100 to 11F when M16 turns on. Logical product of the 32-bit data of D0 and 1 and DAND D108 the 32-bit data of D108 and 109 is performed and...
Page 210: 32-Bit Data Logical Add (Wor, Worp, Dor, Dorp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.1.2 16-, 32-bit data logical add (WOR, WORP, DOR, DORP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) (D1) Indicates the instruction symbol. Operation commands WOR, DOR Setting data Data for which logical add will be performed or head...
Page 211 7. APPLICATION INSTRUCTIONS MELSEC-A (2) Performs the logical add of the 16-bit data of device specified at (S1) and the 16-bit data of device specified at (S2) per bit, and stores the result into the device specified at (D1). 16 bits Before execution After execution (3) As for bit devices, data of them below digit specification is operated as 0.
Page 212 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples (1) Program which performs logical add of the data of D10 and that of D20, and stores the result to D10 when XA turns on. • Coding X00A X00A WORP (2) Program which performs logical add of the data of X10 to 1B and the data of D33, and sends the result to the Y30 to 3F when XA turns on.
Page 213 7. APPLICATION INSTRUCTIONS MELSEC-A (1) Program which performs logical add of the 32-bit data of X0 to 1F and the hexadecimal number of F0FF and stores the result to D66 and 67 when XB turns on. X008 Hexadecimal number of F0FF is stored into D66 DMOV 0000F0FF...
Page 214: 32-Bit Data Exclusive Logical Add (Wxor, Wxorp, Dxor, Dxorp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.1.3 16-, 32-bit data exclusive logical add (WXOR, WXORP, DXOR, DXORP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) WXOR (S1) (S2) (D1) DXOR Operation commands Indicates the instruction symbol. WXOR, DXOR Setting data Data for which exclusive...
Page 215 7. APPLICATION INSTRUCTIONS MELSEC-A (2) Performs the exclusive OR of the 16-bit data of device specified at (S1) and the 16-bit data of device specified at (S2) per bit, and stores the result into the device specified at (D). 16 bits Before execution WXOR After execution...
Page 216 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples WXOR (1) Program which performs exclusive OR of the data of D10 and that of D20, and stores the result to D10 when XA turns on. • Coding X00A X00A WXOR WXORP D20 (2) Program which performs the exclusive OR of the data of X10 to 1B and data of D33, and sends the result to the Y30 to 3B when XA turns on.
Page 217 7. APPLICATION INSTRUCTIONS MELSEC-A DXOR (1) Program which compares the 32-bit data of X20 to 3F and the bit pattern of data of D9 and 10, and stores the number of different bits to D16 when X6 turns on. X006 Exclusive OR of the 32-bit data of X20 to 3F and DXOR X020...
Page 218: 16, 32-Bit Data Not Exclusive Logical Add (Wxnr, Wxnrp, Dxnr, Dxnrp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.1.4 16, 32-bit data NOT exclusive logical add (WXNR, WXNRP, DXNR, DXNRP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) WXNR (S1) (S2) (D1) DXNR Operation commands Indicates the instruction symbol. WXNR, DXNR Setting data Data for which exclusive...
Page 219 7. APPLICATION INSTRUCTIONS MELSEC-A (2) Performs the exclusive NOR of the 16-bit data of device specified at (S1) and the 16-bit data of device specified at (S2) and stores the result into the device specified at (D). 16 bits Before execution WXNR After execution (3) As for bit devices, data of them below digit specification is operated as 0.
Page 220 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples WXNR (1) Program which compares the bit pattern of the 16-bit data of X30 to 3F and that of the 16-bit data of D99 and stores the number of the same bit patterns and the number of different bit patterns to D7 and 8, respectively, when XC turns on.
Page 221 7. APPLICATION INSTRUCTIONS MELSEC-A DXNR (1) Program which compares the bit pattern of the 32-bit data of X20 to 3F and that of the data of D16 and 17, and stores the number of the same bit patterns to D18 when X6 turns on. X006 Exclusive NOR of the 32-bit data of X20 to 3F DXNR...
Page 222: Bin 16-Bit Data 2'S Complement (Neg, Negp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.1.5 BIN 16-bit data 2’s complement (NEG, NEGP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) K1 to 2’s complement execution commands Setting data Head number of device which stores data for which 2’s complement will be performed...
Page 223 7. APPLICATION INSTRUCTIONS MELSEC-A Program Example (1) Program which calculates "D10 - D20" when XA turns on, and obtains the absolute value when the result is negative. X00A When D10 < D20, M3 turns on. < X00A D10 – D20 is executed. When M3 is on, absolute value (2’s complement) is obtained.
Page 224: Rotation Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.2 Rotation Instructions The rotation instructions rotate the data stored in the accumulator. Instruction Instruction Classification Ref. Page Classification Ref. Page Symbol Symbol 7-23 7-25 RORP 7-23 ROLP 7-25 7-23 7-25 RCRP 7-23 RCLP 7-25 Right rotation Left rotation DROR 7-27...
Page 225: 16-Bit Data Right Rotation (Ror, Rorp, Rcr, Pcrp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.2.1 16-bit data right rotation (ROR, RORP, RCR, PCRP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Right rotation commands Indicates the instruction symbol. ROR, RCR Setting data Number of times (0 to 15) Functions Rotates the data of A0 "n"...
Page 226 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples Program which rotates the contents of A0 three bits to the right when XC turns on. • Coding X00C X00C RORP To B15 Before execution Carry flag Contents of B0 (M9012) before execution (n = 1) To B15 Contents of B0 Progress...
Page 227: 16-Bit Data Left Rotation (Rol, Rolr, Rcl, Rclp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.2.2 16-bit data left rotation (ROL, ROLR, RCL, RCLP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Left rotation commands Indicates the instruction symbol. ROL, RCL Setting data Number of times (0 to 15) Functions Rotates the data of A0 "n"...
Page 228 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples Program which rotates the contents of A0 three bits to the left when XC turns on. • Coding X00C ROLP Carry flag (M9012) Before execution Contents of B15 To B0 before execution (n = 1) Contents of B15 Progress To B0...
Page 229: 32-Bit Data Right Rotation (Dror, Drorp, Drcr, Drcrp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.2.3 32-bit data right rotation (DROR, DRORP, DRCR, DRCRP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Right rotation commands Indicates the instruction symbol. DROR, DRCR Setting data Number of times (0 to 31) Functions DROR...
Page 230 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples DROR Program which rotates the contents of A0 and 1 three bits to the right when XC turns • Coding X00A X00A DMOV DMOVP K1 X00C X00C DROR DRORP K3 Before execution To B31 Contents of B0 Carry flag before execution...
Page 231: 32-Bit Data Left Rotation (Drol, Drolp, Drcl, Drclp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.2.4 32-bit data left rotation (DROL, DROLP, DRCL, DRCLP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Left rotation commands Indicates the instruction symbol. DROL, DRCL Setting data Number of times (0 to 31) Functions DROL...
Page 232 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples DROL Program which rotates the contents of A0 and 1 three bits to the left when XC turns • Coding X00A X00A DMOV 80000000 DMOVP H80000000 X00C X00C DROL DROLP K3 Before To B0 Contents of execution Carry flag...
Page 233: Shift Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.3 Shift Instructions The shift instructions perform the shifting of data. Instruction Instruction Classification Ref. Page Classification Ref. Page Symbol Symbol 7-32 7-32 SFRP 7-32 SFLP 7-32 BSFR 7-35 BSFL 7-35 Right shift Left shift BSFRP 7-35 BSFLP 7-35...
Page 234: 16-Bit Data N-Bit Right Shift, Left Shift (Sfr, Sfrp, Sfl, Sflp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.3.1 16-bit data n-bit right shift, left shift (SFR, SFRP, SFL, SFLP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) K1 to Shift commands Indicates the instruction symbol. SFR, SFL Setting data Head number of device...
Page 235 7. APPLICATION INSTRUCTIONS MELSEC-A (1) Shifts the 16-bit data of device specified at (D) to the left by "n" bits. "n" bits, which begin with the lowest bit, change to 0. Before execution Carry flag (M9012) After execution 0 is entered (2) In regards to T/C, the present value (count value) is shifted.
Page 236 7. APPLICATION INSTRUCTIONS MELSEC-A Program which shifts the data of M6 to 13 two bits to the left when X8 turns on. • Coding X008 X008 SFLP K2M6 Specification range of SFLP Before execution Carry flag (M9012) After execution 7 − 34...
Page 237: N-Bit Data 1-Bit Right Shift, Left Shift (Bsfr, Bsfrp, Bsfl, Bsflp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.3.2 n-bit data 1-bit right shift, left shift (BSFR, BSFRP, BSFL, BSFLP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Shift commands Indicates the instruction symbol. BSFR, BSFL Setting data Head number of device which stores data to be...
Page 238 7. APPLICATION INSTRUCTIONS MELSEC-A Execution Conditions Shift command Executed Executed per scan per scan Executed Executed only once only once Operation Error In the following case, operation error occurs and the error flag turns on. • "n" is a negative value. Program Examples BSFR Program which shifts the data of M668 to 676 to the right when X8F turns on.
Page 239: N-Word Data 1-Word Right Shift, Left Shift (Dsfr, Dsfrp, Dsfl, Dsflp)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.3.3 n-word data 1-word right shift, left A1FX A2USH board A0J2H A52G board Applicable AnSH QCPU-A shift (DSFR, DSFRP, DSFL, DSFLP) (A Mode) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Shift commands...
Page 240 7. APPLICATION INSTRUCTIONS MELSEC-A (2) The lowest bit changes to 0. (3) In regards to T/C, the present value (count value) is shifted. (The shift of set value cannot be performed.) Execution Conditions Shift command Executed Executed per scan per scan Executed Executed only once...
Page 241 7. APPLICATION INSTRUCTIONS MELSEC-A DSFL Program which shifts the contents of D683 to 689 to the left when XB turns on. • Coding X00B X00B DSFL D683 DSFLP D683 Specification range of DSFRP instruction Before execution After execution 7 − 39...
Page 242: Data Processing Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.4 Data Processing Instructions The data processing instructions perform operations such as the search, decode, and encode of data. Classification Instruction Symbol Ref. Page 7-41 Search SERP 7-41 7-43 SUMP 7-43 Bit check DSUM 7-43 DSUMP 7-43 DECO 7-46...
Page 243: 16-Bit Data Search (Ser, Serp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.4.1 16-bit data search (SER, SERP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) (S1) (S2) Search commands Setting data Search data or the first (S1) (S2) device number (S1) devices...
Page 244 7. APPLICATION INSTRUCTIONS MELSEC-A Operation Error In the following case, operation error occurs and the error flag turns on. • When "n" points are searched beginning with (S2), the specified device range is exceeded. Program Example Program which compares the data of D883 to 887 with 123 when XB turns on. •...
Page 245: 32-Bit Data Bit Check (Sum, Sump, Dsum, Dsump)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.4.2 16-, 32-bit data bit check (SUM, SUMP, DSUM, DSUMP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) K1 to K1 to DSUM (S) Operation commands Indicates the instruction symbol. SUM, DSUM Setting data Head number of device...
Page 246 7. APPLICATION INSTRUCTIONS MELSEC-A Execution Conditions Operation command Executed Executed per scan per scan Executed Executed only once only once Program Examples Program which obtains the number of bits, which are on (1), in the data of X30 to 3F when X8 turns on.
Page 247 7. APPLICATION INSTRUCTIONS MELSEC-A Transfer by MOVP instruction Addition by +P instruction Number of data which are on among X20 to 5B 7 − 45...
Page 248: 256-Bit Decode, Encode (Deco, Decop, Enco, Encop)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.4.3 8 ↔ 256-bit decode, encode (DECO, DECOP, ENCO, ENCOP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) DECO ENCO Indicates the instruction symbol. Decode, encode commands DECO, ENCO Setting data Decode, encode data or head device number...
Page 249 7. APPLICATION INSTRUCTIONS MELSEC-A ENCO 256 → 8 bit decode (1) A binary value corresponding to the bit, which is 1 in 2n bit data of (S), is stored in (D). 6 5 4 3 2 1 0 1 0 0 0 0 0 0 (Binary value=6) 1 1 0 (2) For "n", 0 to 8 can be specified.
Page 250 7. APPLICATION INSTRUCTIONS MELSEC-A ENCO • Coding X00C X00C ENCO M10 ENCOP M10 CIRCUIT END When 8 is specified as effective bits, 256 points are occupied. When 3 is specified as effective bits, 8 points are occupied. Device D8 Encode result Which point, counting from M10, is on is stored in BIN.
Page 251: Segment Decode (Seg)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS 7.4.4 7 segment decode A2USH-S1 A1FX A2USH board A0J2H (SEG) Applicable A52G boad AnSH QCPU-A (A Mode) Remark * Valid only when special relay M9052 is OFF. The SEG instruction for the CPUs except An changes in function depending on the status of special relay M9052, as follows.
Page 252 7. APPLICATION INSTRUCTIONS MELSEC-A (4) For the seven-segment display data, refer to the below. Execution Conditions Decode command Executed Executed per scan per scan Configuration of Displayed Hexadecimal 7-segment Data Bit pattern number 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...
Page 253 7. APPLICATION INSTRUCTIONS MELSEC-A Program Example Program which converts the data of XC to F to seven-segment display data and sends the display data to Y38 to 3F when X0 turns on. • Coding X000 X000 X00C Y038 K1X00C K2Y038 Y38 to 3F *Y38 to 3F do not change until the next data is output.
Page 254: Word Device Bit Set, Reset (Bset, Bsetp, Brst, Brstp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.4.5 Word device bit set, reset (BSET, BSETP, BRST, BRSTP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Set/reset commands Indicates the instruction symbol. BSET, BRST Setting data Device number for bit set, reset Bit number for bit set,...
Page 255 7. APPLICATION INSTRUCTIONS MELSEC-A BRST (1) Resets (0) the "n"th bit of word device specified at (D). (2) For "n", 0 to 15 are effective. When 15 is exceeded, the instruction is executed at the lower four bits. BRST D10 Before execution After execution Set to 0.
Page 256: 16-Bit Data Dissociation, Association (Dis, Disp, Uni, Unip)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.4.6 16-bit data dissociation, association (DIS, DISP, UNI, UNIP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Indicates the instruction symbol. DIS, UNI Setting data Dissociation/association commands • First device number of devices where data to be dissociated is stored •...
Page 257 7. APPLICATION INSTRUCTIONS MELSEC-A (4) When "n" is 0, no processing is performed and the contents of "n" points beginning with the device of (D) do not change. (1) Associates the data of lower four bits of 16-bit data in devices of "n" points, which begin with the device specified at (S), to the 16-bit device specified at (D).
Page 258 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples Program which stores the 16-bit data of D0 to the D10 to 13 per four bits when X0 turns on. • Coding X000 X000 DISP Before execution After execution Set to 0. Storage area Program which stores the lower four-bit data of D0 to 2 to the D10 when X0 turns on.
Page 259: Ascii Code Conversion (Asc)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.4.7 ASCII code conversion (ASC) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Conversion command Setting data Head number of device ASCII characters (8 characters) which will store ASCII code Function Converts the specified alphanumeric characters into the ASCII code and stores the...
Page 260 7. APPLICATION INSTRUCTIONS MELSEC-A Program Example Program which converts "ABCDEFGHIJKLMNOP" into the ASCII code and stores the result to the D88 to 95 when X8 turns on, and displays the ASCII data of D88 to 95 at the LED indicator on the front face of CPU when X16 turns on. X008 Eight characters, A to H, are converted into ASCII ABCDEFGH...
Page 261: Fifo Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.5 FIFO Instructions The FIFO instructions perform the write and read of data to and from the FIFO table. Classification Instruction Symbol Ref. Page FIFW 7-60 Write FIFWP 7-60 FIFR 7-60 Read FIFRP 7-60 7 − 59...
Page 262: Fifo Table Write, Read (Fifw, Fifwp, Fifr, Fifrp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.5.1 FIFO table write, read (FIFW, FIFWP, FIFR, FIFRP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) FIFW FIFR Indicates the instruction symbol. Read commands FIFW, FIFR Setting data •...
Page 263 7. APPLICATION INSTRUCTIONS MELSEC-A FIFR (1) Reads data from the first device after the pointer of FIFO table and stores the data into the of (S). (2) The data of data table is shifted to the front one by one and the preceding data is set to 0.
Page 264 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples FIFW Program which uses D38 to 47 as a FIFO table and temporarily stores the data of X20 to 2F when XB turns on. When the data exceeds 9, this program turns on Y60 to disable the execution of FIFW instruction.
Page 265 7. APPLICATION INSTRUCTIONS MELSEC-A FIFR Program which reads data from D38 to 45 of the FIFO table when XB turns on, and outputs the data to the Y30 to 3F. (Data is read as shown below when the pointer value is 7.) When pointer (D38) is 0, Y60 is Y060 turns on.
Page 266: Buffer Memory Access Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.6 Buffer Memory Access Instructions Buffer memory access instructions are used to read and write data of buffer memory of special function modules and remote terminal modules (when the A2C, A52G is used). There are 16 types of buffer memory access instructions as shown below. Classification Instruction Symbol Ref.
Page 267: Special Function Module 1-, 2-Word Data Read (From, Fromp, Dfro, Dfrop)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.6.1 Special function module 1-, 2-word AnU, A2AS A2USH-S1 A1FX A2USH board A0J2H data read (FROM, FROMP, DFRO, Applicable A52G board AnSH QCPU-A (A Mode) DFROP) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *1: Bit devices cannot be used with the An and A3H CPUs.
Page 268 7. APPLICATION INSTRUCTIONS MELSEC-A DFRO Reads the data of "n3×2" words, which start at the address specified at "n2" of buffer memory inside the special function module specified at "n1", and stores the data into devices which begin with the device specified at (D). Special function module buffer memory Device specified at (D)
Page 269 7. APPLICATION INSTRUCTIONS MELSEC-A DFRO Program which reads the data of two words from the address 10 of buffer memory of A68AD, loaded in I/O numbers 040 to 05F to D0 and 1. • Coding X000 X000 DFRO 0004 DFRO H0004 POINT If a FROM instruction is executed for a special function module frequently in a...
Page 270: Special Function Module 1-, 2-Word Data Write (To, Top, Dto, Dtop)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.6.2 Special function module 1-, 2-word A1FX A2USH board A0J2H A52G board Applicable AnSH QCPU-A data write (TO, TOP, DTO, DTOP) (A Mode) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *1: Bit devices cannot be used with the An and A3H.
Page 271 7. APPLICATION INSTRUCTIONS MELSEC-A Writes the data of "n3×2" points, which begin with the device specified at (S), to addresses starting at the address specified at "n2" of buffer memory inside the special function module specified at "n1". Special function module buffer memory CPU module Device specified at (S)
Page 272 7. APPLICATION INSTRUCTIONS MELSEC-A Operation Errors In the following cases, operation error occurs and the error flag turns on. • Access cannot be made to the special function module. • The I/O number specified at "n1" is not a special function module. •...
Page 273: (From, Prc, Fromp, Prc, Dfro, Prc, Dfrop, Prc)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.6.3 Remote terminal module 1- and A1FX A2USH board A0J2H Applicable A52G board AnSH QCPU-A 2-word data read (A Mode) (FROM, PRC, FROMP, PRC, DFRO, PRC, DFROP, PRC) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level...
Page 274 7. APPLICATION INSTRUCTIONS MELSEC-A DERO , (1) Reads data of "n3×2" words which begin with the address specified at "n2" of buffer memory in the remote terminal module specified at "n1", and stores the data in the devices starting with the one specified at (D1). Remote terminal buffer memory Device specified...
Page 275 7. APPLICATION INSTRUCTIONS MELSEC-A (3) Though the data specified at (D3) is dummy data which calls for no processing in the program, specify any output (Y) number at this. Devices specified at (D3) can be freely used in the program. (4) Data communication is performed according to the data in the communication request registration areas which are registered by executing the FROM(P) and DFRO(P) instructions, as shown below.
Page 276 7. APPLICATION INSTRUCTIONS MELSEC-A (8) Status of registration in the communication request registration areas can be confirmed by M9081 and D9081. M9081: Turns ON when the communication request registration areas are full. Turns OFF when there is a vacant area. D9081: Stores the number of vacant areas in the communication request registration areas.
Page 277 7. APPLICATION INSTRUCTIONS MELSEC-A DFRO , A program which reads data of 2 words from address 14 of buffer memory of the AD61C (head station number 1) to D10 and D11 when X0 is turned ON. X000 DFRO 1 ……... M0 turns ON when communication Y000 processing is completed.
Page 278: (To, Prc, Top, Prc, Dto, Prc, Dtop, Prc)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.6.4 Remote terminal module 1- and A2USH board A1FX A0J2H Applicable A52G board AnSH QCPU-A 2-word data write (A Mode) (TO, PRC, TOP, PRC, DTO, PRC, DTOP, PRC) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level...
Page 279 7. APPLICATION INSTRUCTIONS MELSEC-A When a constant is designated to (S), writes the same data (value designated to (S)) to the area of n3 points starting from the specified buffer memory. ((S) can be designated in the following range: -32768 to 32767 or 0 to FFFF Remote terminal buffer memory...
Page 280 7. APPLICATION INSTRUCTIONS MELSEC-A REMARK The method for specifying "n1" for an A2C is different from that for an A52G as mentioned below. 1) A2C: Head station number of remote terminal modules is specified at "n1". Station Station No. 1 No.
Page 281 7. APPLICATION INSTRUCTIONS MELSEC-A (4) Data communication is performed according to the data in the communication request registration areas which are registered by executing the TO(P) and DTO(P) instructions, as shown below. Execution of these instructions is completed when data are registered in the communication request registration areas.
Page 282 7. APPLICATION INSTRUCTIONS MELSEC-A (9) If the TO(P)/DTO(P) instructions are executed to a remote terminal module which is communicating with other module, execution of the instructions is again performed to the same remote terminal module immediately after the processing being executed. Execution Conditions Read command Executed every...
Page 283 7. APPLICATION INSTRUCTIONS MELSEC-A DTO , A program which writes content of D1000 to address 5 and content of D1001 to address 6 of buffer memory of the AD61C (head station number 1) when X0 is turned ON. X000 D1000 1 ……...
Page 284: (From, Fromp, Dfro, Dfrop)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.6.5 Special module/special block A1FX A2USH board A0J2H Applicable A52G board AnSH QCPU-A 1-, 2-word data read (A Mode) (FROM, FROMP, DFRO, DFROP) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *: K1 to K4 when the FROM(P) instruction is used.
Page 285 7. APPLICATION INSTRUCTIONS MELSEC-A DFRO Reads the (n3×2) words of data from the buffer memory address specified by n2 in the special module/special block specified by n1 and writes the data to the A1FXCPU beginning with the device number specified by (D). Buffer memory in Device number the special module/...
Page 286 7. APPLICATION INSTRUCTIONS MELSEC-A Program Example FROM The program to read 1-word data from K2000 of buffer memory in the second special module/special block from the A1FXCPU and writes the read data to D0 when X20 is turned ON. X020 FROM 0001 2000...
Page 287 7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS 7.6.6 Special module/special block A2USH-S1 A1FX A2USH board A0J2H Applicable A52G board AnSH QCPU-A 1-, 2-word data write (A Mode) (TO, TOP, DTO, DTOP) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *: K1 to K4 when the TO(P) instruction is used.
Page 288 7. APPLICATION INSTRUCTIONS MELSEC-A When a constant is designated to (S), writes the same data (value designated to (S)) to the area of n3 points starting from the specified buffer memory. ((S) can be designated in the following range: -32768 to 32767 or 0 to FFFF Buffer memory in the special module/...
Page 289 7. APPLICATION INSTRUCTIONS MELSEC-A Operation Errors In the following cases, operation error occurs and the error flag turns on. • Access to a special module/special block is not possible. • n1 designation is other than 0 to 7 • When "n3" points which start with the device specified at (S) exceed the specified device range.
Page 290: For To Next Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.7 FOR to NEXT Instructions Applicable All CPUs 7.7.1 FOR to NEXT (FOR, NEXT) Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Repeat program NEXT Functions (1) When the processing of FOR to NEXT instructions is executed "n" times unconditionally, performs the processing of the next step to the NEXT Instruction.
Page 291 7. APPLICATION INSTRUCTIONS MELSEC-A (4) Up to five levels of the nesting of FOR is allowed. X000 X001 Up to five levels of the nesting of FOR is allowed. X002 NEXT NEXT NEXT Operation Errors In the following cases, operation occurs and the PC stops its operation. •...
Page 292: Local, Remote I/O Station Access Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.8 Local, Remote I/O Station Access Instructions Local, remote I/O station access instructions are used to transfer data in a data link system. Four instructions are provided as shown below. The local and remote I/O station access instructions can be used in the sequence program of the master station only.
Page 293: Local Station Data Read, Write (Lrdp, Lwtp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.8.1 Local station data read, write (LRDP, LWTP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Setting data Local station number Read command Head device number of local LRDP station to be read LRDP...
Page 294 7. APPLICATION INSTRUCTIONS MELSEC-A (3) It is impossible to execute 2 or more LRDP instructions simultaneously or to execute the LRDP instruction and the LWTP instruction simultaneously to one local station. POINT Provide interlock using M9200, M9201, M9202 and M9203 so that the LRDP instruction and/or the LWTP instruction may not be executed during the data read from local stations by the LRDP instruction.
Page 295 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples LRDP A program to store data of D3 to D8 of the 3rd local station in D99 to D104 of the master station when X3 is ON. Provide interlock using If the LWTP instruction is used to the same station, Use a pulse signal for the LRDP instruction provide interlock using the LWTP instruction execution flag.
Page 296 7. APPLICATION INSTRUCTIONS MELSEC-A LWTP (1) Stores the data of "n2" points, which begin with the device specified at (S) of master station, to devices, which begin with the device specified at (D) , of local station specified at "n1". Local station No.
Page 297 7. APPLICATION INSTRUCTIONS MELSEC-A Execution Conditions Write command LWTP Executed only once Operation Errors In the following cases, operation error occurs and the error flag turns on. • The station number specified at "n1" is not a local station. • "n2" points starting at (D) exceed the specified device range. •...
Page 298 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples LWTP A program to store data of D99 to D104 of the master station in D3 to D8 of the 3rd local station when X3 is ON. Provide interlock using Use a pulse signal for the LWTP instruction If the LRDP instruction is used to the same station, this command.
Page 299: Remote I/O Station Data Read, Write (Rfrp, Rtop)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.8.2 Remote I/O station data read, write A1FX A2USH board A0J2H A52G board Applicable AnSH QCPU-A (RFRP, RTOP) (A Mode) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Setting data Head I/O number of special function module specified by...
Page 300 7. APPLICATION INSTRUCTIONS MELSEC-A Functions RFRP (1) Stores data of "n3" points from the address specified at "n2" of buffer memory in the special function module specified at "n1" (the I/O number in the remote I/O station assigned by the master station) in the link registers starting with the one specified at (D) of the master station.
Page 301 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples RFRP A program to read data of 10 points starting with address 10 of the A68AD which is loaded in the slot for the remote station of which I/O numbers are 140 to 15F to W52 to 61 when X3 is ON.
Page 302 7. APPLICATION INSTRUCTIONS MELSEC-A CAUTION Provide interlock using the special registers mentioned below so that the RTOP instruction may be executed when the data link with remote I/O stations is normal and parameter communication is not being performed. Remote I/O station normal/error judgment: D9228 to D9231 Parameter communication execution/non-execution judgment: D9224 to D9227 For details, refer to the type MELSECNET, MELSECNET/B Data Link System Reference Manual (IB(NA)-66350).
Page 303 7. APPLICATION INSTRUCTIONS MELSEC-A Execution Conditions Read command RFRP Executed only once Operation Errors In the following cases, operation error occurs and the error flag turns on. • The specified station is not a remote station. • The head I/O number specified at "n1" is not a special function module. •...
Page 304 7. APPLICATION INSTRUCTIONS MELSEC-A • Coding X003 Executed only once. Turned OFF by the Y14F sequence program. X15F Y14E Turned ON by the special X15E Turned OFF by the function module. RTOP H0140 W052 sequence program. Y10E Turned ON by the special X15F function module.
Page 305 7. APPLICATION INSTRUCTIONS MELSEC-A POINT The area equal to the number of special function modules, which are loaded to corresponding remote I/O station, starting with the head device number of the master to remote I/O station link registers set with link parameters is used by PC CPU OS.
Page 306: Display Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.9 Display Instructions (1) Display instructions are used to output ASCII codes to the output modules, to display data on the LED display on the front panel of the CPU module and to reset the annunciator. (2) The display instructions are available in the following seven types.
Page 307 7. APPLICATION INSTRUCTIONS MELSEC-A (5) When the display instruction is executed, the display is as shown below. Display 16 characters 16 characters are displayed at the LED indicator by LED instruction. First half 8 characters Latter half 8 characters The first half 8 characters are displayed at the LED indicator by Blank LEDA instruction.
Page 308: Ascii Code Print Instructions (Pr, Prc)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.9.1 ASCII code print instructions A1FX A2USH board A0J2H A52G board Applicable AnSH QCPU-A (PR, PRC) (A Mode) Remark * With a PR instruction, only output of 16 characters in the ASCII code is possible. Available Device Bit device Word (16-bit) device...
Page 309 7. APPLICATION INSTRUCTIONS MELSEC-A (1) ASCII code output of 16 characters 1) The number of points used for the output module is 10 points which start at the Y number specified at (D). Device which store ASCII code Upper 8 bits Lower 8 bits Output Y Head of...
Page 310 7. APPLICATION INSTRUCTIONS MELSEC-A (2) ASCII code output up to 00H code (Unusable with the An and A3V.) 1) The number of points used for the output module is 10 points which start at the Y number specified at (D). Device which store ASCII code Upper 8 bits Lower 8 bits...
Page 311 7. APPLICATION INSTRUCTIONS MELSEC-A (1) Outputs the comment (ASCII code) of the device specified at (S) to the output module specified at (D). The number of points used for the output module is eight points which start at the Y number specified at (D). Comment of ×1 Output Y Head of output...
Page 312 7. APPLICATION INSTRUCTIONS MELSEC-A Execution conditions ASCII print command Executed only once Program Examples Program which converts “ABCDEFGHIJKLMNOP” into an ASCII code and stores the code into the D0 to 7 when X0 turns on, and outputs the ASCII code of D0 to 7 into the Y14 to 1D when X1 turns on.
Page 313 7. APPLICATION INSTRUCTIONS MELSEC-A • Coding *: When a CPU other than An X000 or A3V is used and M9049 is ABCDEFGH OFF, 00 must be specified IJKLMNOP in D8 in this example as an MOVP error will result without the NUL (00 ) code.
Page 314 7. APPLICATION INSTRUCTIONS MELSEC-A • Coding X000 Y035 Y035 Y060 X003 Y035 When comment of Y35 is ASCII code Strobe signal PRC instruction PRC instruction execution execution flag 7 − 112...
Page 315: Ascii Code Comment Display Instructions (Led, Ledc)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.9.2 ASCII code comment display A2USH board A1FX A0J2H Applicable A52G board AnSH QCPU-A instructions (LED, LEDC) (A Mode) *1: A3N only. *3: A3A only. Remark *2: A3 only. *4: A3U and A4U only. Available Device Bit device Word (16-bit) device...
Page 316 7. APPLICATION INSTRUCTIONS MELSEC-A (3) For ASCII characters which can be displayed, refer to (3) in the section of the LEDC instruction. (4) For the conversion of alphanumeric characters into ASCII data in a sequence program, use the ASC instruction. LEDC (1) Displays the comment (15 characters) of device specified at (S) at the LED indicator on the front of CPU.
Page 317 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples Program which converts "ABCDEFGHIJKLMNOP" into ASCII code and stores it to the D88 to 95 when X8 turns on, and displays the ASCII data of D88 to 95 at the LED indicator on the front face of CPU when X16 turns on. X008 Eight characters, A to H, are converted into ASC ABCDEFGH D88...
Page 318: Character Display Instructions (Leda, Ledb)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.9.3 Character display instructions A2USH board A1FX A0J2H Applicable A52G board AnSH QCPU-A (LEDA, LEDB) (A Mode) *1: A3N only. Remark *2: A3 only. The LEDA/LEDB instructions are used as the starting command for the dedicated instructions for the AnA, A2AS, AnSH, AnU, QCPU-A (A Mode) and A2USH board.
Page 319 7. APPLICATION INSTRUCTIONS MELSEC-A Execution Conditions Display command LEDA LEDB Executed Executed only once only once Program Examples LEDA LEDB Program which displays "ABCDEFGHIJKLMNOP" at the LED indicator on the CPU front when XC turns on. X00C First half 8 characters are specified. LEDA ABCDEFGH Last half 8 characters are specified.
Page 320: Annunciator Reset Instruction (Ledr)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.9.4 Annunciator reset instruction (LEDR) Applicable All CPUs In the case of the CPU modules which have an LED indicator on its front side, pressing the "INDICATOR RESET" switch executes the processing same as that called by the LEDR instruction. Available Device Bit device Word (16-bit) device...
Page 321 7. APPLICATION INSTRUCTIONS MELSEC-A Before After execution execution -1 is reduced Number of entered F numbers (annunciaor accumulator) F number storage area CPU modules which have an LED indicator on the front panel Performs the following actions: (1) Resets the F number displayed at the CPU front. (2) Resets the annunciator (F) stored in D9009.
Page 322 7. APPLICATION INSTRUCTIONS MELSEC-A Execution Conditions Reset command LEDR Executed Executed only one only one POINT The LEDR instruction is used as the end command for the extended application instructions for the AnA (-F) and AnU. For details, refer to the AnSHCPU/AnACPU/AnUCPU Programming Manual (Dedicated Instructions).
Page 323: Other Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.10 Other Instructions Instructions which perform operations such as the reset of WDT, the failure check, and the set and reset of carry flag. Classification Instruction Symbol Ref. Page WDT reset 7-122 Failure check 7-124 7-131 Status latch Reset SLTR...
Page 324: Wdt Reset (Wdt, Wdtp)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.10.1 WDT reset (WDT, WDTP) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) WDT reset commands WDTP Functions (1) Resets the watch dog timer in a sequence program. (2) Used when the period of time from step 0 to END (FEND) in the sequence program exceeds the set value of watch dog timer depending on conditions.
Page 325 7. APPLICATION INSTRUCTIONS MELSEC-A (5) Values of scan time stored in special registers D9017 to D9019 and D9021 are not cleared though the WDT or WDTP instruction is executed. Values of special registers may therefore become larger than the WDT values set with parameters (the A3H, A3M and AnA, A2AS and AnU use fixed WDT values).
Page 326: Specific Format Failure Check (Chk)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS 7.10.2 Specific format failure check (CHK) A2USH-S1 A2USH board A1FX A0J2H Applicable A52G board AnSH QCPU-A (A Mode) Remark * Valid only when the input/output control method is direct method. The CHK instruction varies in function with I/O control mode as shown below. I/O control mode Refresh mode Direct mode...
Page 327 7. APPLICATION INSTRUCTIONS MELSEC-A Functions (1) The CHK instruction is used for error check of a circuit which is to detect abnormality in reciprocating movements provided with sensors on both stroke ends as shown below. If an error is detected, (D1) is turned ON, and the error code is stored in (D2).
Page 328 7. APPLICATION INSTRUCTIONS MELSEC-A 2) The internal relay of which number (Y ) is same as the contact number (X ) of forward stroke end sensors must be controlled as follows. In forward run: Turn it ON. In backward run: Turn it OFF. (2) The CHK instruction executes processing equivalent to the circuit shown below with one specified contact.
Page 329 7. APPLICATION INSTRUCTIONS MELSEC-A (3) Devices (D1) and (D2) must be reset before execution of the CHK instruction. If devices (D1) and (D2) are not reset after execution of the CHK instruction, the CHK instruction cannot be executed again. (Contents of (D1) and (D2) are retained till they are reset by the sequence program.) (4) Always provide pointer P254 to the head of the CHK instruction block.
Page 330 7. APPLICATION INSTRUCTIONS MELSEC-A (8) Error codes stored in (D2) by the CHK instruction vary with conditions establish-ed as shown below. P254 (D1) (D2) Contact Contact Contact Contact Contact Contact No. 1 No. 50 No. 51 No. 100 No. 101 No.
Page 331 7. APPLICATION INSTRUCTIONS MELSEC-A List of Error Code Numbers (Error codes are stored by BCD.) Priority High Order of contact points Error Code Numbers for the CHK Instruction Execution The CHK instruction is executed every scan regardless of ON/OFF status of check Conditions condition contact points.
Page 332 7. APPLICATION INSTRUCTIONS MELSEC-A Operation Errors In the following cases, operation error occurs and the PC CPU stops operation. • When parallel circuits are provided: Bit device specified at (D1). P∗∗ Label CHK (D1) (D2) Eliminate parallel contacts. P254 P∗∗ Eliminate parallel contacts in the circuit block of CJ.
Page 333: Status Latch Set, Reset (Slt, Sltr)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS 7.10.3 Status latch set, reset A2USH-S1 A2USH board A1FX A0J2H (SLT, SLTR) Applicable A52G board AnSH QCPU-A (A Mode) *1: Unusable with A1N. Remark *2: Unusable with A1. Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011)
Page 334 7. APPLICATION INSTRUCTIONS MELSEC-A Execution Conditions Status latch command Reset command Executed only once Executed only once SLTR Executed only once POINT When the status latch (SLT) instruction is executed, the scan time of program- mable controller CPU increases as shown in the following table. Latch of Only Latch of Both Device Device Memory...
Page 335: Sampling Trace Set, Reset (Stra, Strar)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS 7.10.4 Sampling trace set, reset A2USH-S1 A1FX A2USH board A0J2H (STRA, STRAR) A52G board Applicable AnSH QCPU-A (A Mode) *1: Unusable with A1N. Remark *2: Unusable with A1. Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011)
Page 336 7. APPLICATION INSTRUCTIONS MELSEC-A STRAR (1) Reset instruction for the STRA instruction. (2) By executing the STRAR instruction, the STRA instruction is enabled again. (3) Turns off M9043. Excecution Conditions Sampling trace command Reset command STRA Executed only once Executed only once STRAR Executed only once 7 −...
Page 337: Carry Flag Set, Reset (Stc, Clc)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.10.5 Carry flag set, reset (STC, CLC) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Carry flag set input Set of carry flag Carry flag reset input Reset of carry flag Functions (1) Sets (turns on) the carry flag contact (M9012).
Page 338 7. APPLICATION INSTRUCTIONS MELSEC-A Program Example STC , CLC Program which performs addition of the BCD data of X0 to F and the BCD data of D0 when M0 turns on, and turns on the carry flag (M9012) when the result is more than 9999, and turns off the carry flag when the result is 9999 or less.
Page 339: Pulse Regeneration Instruction (Duty)
7. APPLICATION INSTRUCTIONS MELSEC-A 7.10.6 Pulse regeneration instruction (DUTY) Applicable All CPUs Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) *1: Index qualification can be used with AnA and AnU only. Setting data Start input Number of scans during which timing pulse is on Number of scans during...
Page 340 7. APPLICATION INSTRUCTIONS MELSEC-A Operation Error In the following case, operation error occurs and the error flag turns on. • The setting of D is other than M9020 to 9024. Program Example DUTY When X8 is turned ON, M9021 turns on for 1 scan and off for 3 scans. X008 DUTY 1 M9021...
Page 341: Servo Program Instructions
7. APPLICATION INSTRUCTIONS MELSEC-A 7.11 Servo Program Instructions Servo program instructions are used with the A73 for start request and data change of servo programs. There are 2 servo program instructions as shown below. Name Symbol Refer to Name Symbol Refer to Start request DSFRP...
Page 342: Servo Program Start (Dsfrp)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS 7.11.1 Servo program start (DSFRP) A2USH-S1 A1FX A2USH board A0J2H A52G board Applicable AnSH QCPU-A (A Mode) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Execution command Setting data Axis number to be started DSFRP Servo program number to...
Page 343 7. APPLICATION INSTRUCTIONS MELSEC-A (3) At (D), set axis numbers to be started in the servo program specified with "n", as shown below. Starting axis numbers • 1 axis : Set for 1 axis. (1 digit) • 2 axes: Set for 2 axes. (2 digits) •...
Page 344 7. APPLICATION INSTRUCTIONS MELSEC-A Operation Errors In the following cases, operation error occurs and the DSFRP instruction is not executed. • (D) is set with 4 digits. • Set value of (D) is other than 1 to 8. • Two same axis numbers are set at (D). •...
Page 345 7. APPLICATION INSTRUCTIONS MELSEC-A (2) A program to execute only once the servo program of which number is specified with the BCD data at X90 to X9F when X80 is ON. (This servo program is to perform 2-axis linear interpolation of axes 1 and 2.) M9036 M2000 PC READY is ON.
Page 346: Present Position Data And Speed Change Instruction (Dsflp)
7. APPLICATION INSTRUCTIONS MELSEC-A AnU, A2AS A2USH-S1 7.11.2 Present position data and speed A2USH board A1FX A0J2H Applicable A52G board AnSH QCPU-A change instruction (DSFLP) (A Mode) Remark Available Device Bit device Word (16-bit) device Constant Pointer Level M9012 (M9010, M9011) Execution command Axis number for present position data/speed...
Page 347 7. APPLICATION INSTRUCTIONS MELSEC-A POINT The DSFLP instruction used with the A73CPU cannot use index qualification for specification of (D) and "n". If the DSFLP instruction with index qualification is executed, operation error will result. (4) Present position data change by the DSFLP instruction is performed as follows. 1) The start enable flag (M200n)* which corresponds to the axis specified with (D) is set.
Page 348 7. APPLICATION INSTRUCTIONS MELSEC-A Operation Errors In the following cases, an operation error occurs and the DSFLP instruction is not executed. (1) Set value of (D) is other than 1 to 8. (2) Set value of "n" is other than 0 TO 4. (When set value of "n"...
Page 349 7. APPLICATION INSTRUCTIONS MELSEC-A Program Examples DSFLP (1) A program to change present position data of axis 2 to the BCD data set at X90 to XAF when X81 is turned ON. X081 The present position data change storage flag (M10) is set when X81 is turned ON.
Page 350 7. APPLICATION INSTRUCTIONS MELSEC-A (2) A program to change positioning speed of axis 2 to the BCD data set at X90 to XAF when X81 is turned ON. X081 The speed change storage flag (M10) is set when X81 is turned ON. The BCD data of X90 to XAF are stored in DBIN X090 D968...
Page 351: Microcomputer Mode
8. MICROCOMPUTER MODE MELSEC-A 8. MICROCOMPUTER MODE This section gives the microcomputer mode specifications, memory map and data memory configuration of the ACPU modules. Note that the AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board cannot use the microcomputer mode. 8.1 Specifications of Microcomputer Mode Table 8.1 Specifications of Microcomputer Mode Microcomputer...
Page 352: Using Utility Program
8. MICROCOMPUTER MODE MELSEC-A 8.2 Using Utility Program Various types of control and operation (e.g. PID control, function operation, code conversion) can be executed by calling the utility program from the microcomputer program area. (1) Utility program entry procedure Combine together the utility program with the user program in the following procedure: Peripheral device with FDD function (e.g.
Page 353 8. MICROCOMPUTER MODE MELSEC-A (2) Calling the utility program Call the utility program from the sequence program as described below: Specify the data required for program run, device number for Specify input data in any …… storing the operation result, etc. in any word device. word device (D, W, R) The head device number storing the input data should be Specify the head device...
Page 354: Using User-Written Microcomputer Programs
8. MICROCOMPUTER MODE MELSEC-A 8.3 Using User-Written Microcomputer Programs A source program written by the user in the 8086 assembly language is converted to a machine language using assembler commands of CP/M or MS-DOS. This converted program is called "the object program" and is to be stored in the microcomputer program area of the CPU using the system floppy disk for a peripheral device which has microcomputer mode.
Page 355 8. MICROCOMPUTER MODE MELSEC-A 4) To return from the microcomputer program to the sequence program, use the RETF (return to outside the segment) instruction. CP/M and CP/M-86 are trademarks of Digital Research, Inc. MS-DOS is a trademark of Microsoft Corporation. (3) Calling method of microcomputer program The microcomputer program is called by the execution of SUB instruction in the sequence program.
Page 356: Memory Map
8. MICROCOMPUTER MODE MELSEC-A POINTS (1) The processing time of a microcomputer program called by one SUB instruction must be 5 msec or less. If it exceeds 5 msec, operation combination between the microcomputer program processing and the internal processing of the PC becomes out of control and the PC cannot run correctly.
Page 357: Differences In Operations Called By Microcomputer Instructions According To Cpu Models
8. MICROCOMPUTER MODE MELSEC-A 8.3.3 Differences in operations called by microcomputer instructions according to CPU models Microcomputer instruction processing operation differs according to the CPU to be used. (1) REP LODSW, REP LODSB instructions (a) AnSHCPU and A1FXCPU Disregarding the value at CX register, the contents of memory indicated by the S1 register are sent only once to AL (8-bit operation) or AX (16-bit operation) register.
Page 358: Configuration Of Data Memory Area
8. MICROCOMPUTER MODE MELSEC-A 8.3.4 Configuration of data memory area The data memory area (8000 to 9FFF ) stores device data. The memory area of each device and its configuration are as indicated below. Device Address Configuration Type 8000 Odd address Even address X0 to FF 803F...
Page 359 8. MICROCOMPUTER MODE MELSEC-A REMARK Communication of input/output information with an input/output module is executed only in the address range indicated below. A1FX: X/Y20 to FF A1SH, A1SJH: X/Y0 to FF A2SH: X/Y0 to 1FF A2SH-S1: X/Y0 to 3FF 8 − 9...
Page 360 8. MICROCOMPUTER MODE MELSEC-A Device Address Configuration Type 8400 Internal relay (M) Latch M/L/S relay (L) 0 to 2047 Step relay (S) 85FF 8600 Link B0 to3FF relay (B) • All devices consist of one bit and store ON/OFF data of device by use of eight 86FF bits at even addresses.
Page 361 8. MICROCOMPUTER MODE MELSEC-A Device Address Configuration Type Data 8800 register 8FFF 1023 Link 9000 register 97FF A2-S1 Present 9800 value of 99FF timer (T) A2NS1 All devices consist of two bytes (16 bits). Example The configuration of D0 is as shown below: A52G Present A0J2H...
Page 362 8. MICROCOMPUTER MODE MELSEC-A Device Address Configuration Type Even address Odd address 8000 8000 8002 8004 Input (X) X0 to 7FF 80FF • Stores ON/OFF data from an input unit, read only. • 0 indicates OFF and 1 ON. Odd address Even address 8200 8202...
Page 363 8. MICROCOMPUTER MODE MELSEC-A Device Address Configuration Type 8740 M9000 Special relay (M) 875F 9255 • Stores device ON/OFF data in one bit locations. 8780 Timer (T) • 0 indicates OFF and 1 ON. T0 to 255 contact 879F Example: M0 to 47 are as follows: Odd address Even address...
Page 364 8. MICROCOMPUTER MODE MELSEC-A Device Address Configuration Type Data 8800 register 8FFF 1023 Link 9000 register 97FF Timer (T) 9800 present value 99FF All devices consist of two bytes (16 bits). Example The configuration of D0 is as shown below: Counter 9A00 present...
Page 365 8. MICROCOMPUTER MODE MELSEC-A Device Address Type File register head address = 20000H + (memory cassette RAM capacity) - (comment capacity) - (file register capacity) Memory cassette RAM capacity A3(N)MCA-0=16K bytes A3(N)MCA-2=16K bytes A3(N)MCA-4=32K bytes A3(N)MCA-8=64K bytes A3MCA-12=96K bytes A3NMCA-16=96K bytes (actual capacity: 128K bytes) File register A3MCA-18=144K bytes A3MCA-24=144K bytes (actual capacity: 192K bytes)
Page 366 8. MICROCOMPUTER MODE MELSEC-A Device Address Type Memory cassette When A3NMCA-24, 40 or 56 is used When A3MCA-16 is used Block No. Head address Block No. Head address A0000 38000 A4000 3C000 A8000 AC000 B0000 A2-S1 B4000 B8000 Extension file register A2N-S1 BC000 C0000...
Page 367 ERROR CODE LIST ERROR CODE LIST If an error occurred when the PC is in RUN mode, error indication is given by self-checking function and corresponding error code and error step are stored in special registers. This section gives description of cause and corrective action for each case of error. Reading Error Codes If an error occurred, corresponding error code can be read from the peripheral.
Page 368: Error Code List
ERROR CODE LIST Table 9.1 Error Code List for the An, AnN, A3H, A3M, A3V, A0J2H, AnS, A2C, A73, A52G, A1FX and A3N board (Continue) Error Code Error Message CPU States Error and Cause Corrective Action (D9008) "CAN’T Stop (1) There is no jump destination or Read the error step by use of peripheral EXECUTE(P)"...
Page 369 Since the program is in an endless lop (Checked due to the instructions, continuously) check the program. "MAIN CPU Stop Main-CPU is out of control or defective. Since this is a CPU hardware error, DOWN" (Sub-CPU checked it.) consult Mitsubishi representative. (Checked continuously) 9 - 3...
Page 370 When the instruction is Since this is an accessed special FROM (Checked at the executed, access has been made to the function module error, consult Mitsubishi execution of special function module but the answer representative. FROM and TO is not given.
Page 371 (2) CPU malfunction due to noise. program, remove it. AnNCPU only (3) Hardware error of CPU module. (2) Take measures against noises. (3) Consult Mitsubishi representative. "BATTERY Continue (1) The battery voltage has dropped to (1) Replace battery. ERROR"...
Page 372: Error Code List For The Anshcpu
ERROR CODE LIST Error Code List for AnSHCPU Table 9.2 shows the error messages, description and cause of error and corrective actions for A1SJH(S8), A1SH and A2SH(S1). Detailed error codes are stored in D9092 only when a dedicated instruction for CC-Link is used. Table 9.2 Error Code List for AnSHCPU Detailed Error...
Page 373 ERROR CODE LIST Table 9.2 Error Code List for AnSHCPU (Continue) Detailed Error Error Error Message Code Error and Cause Corrective Action Code States (D9008) (D9092) — Stop (1) There is no jump destination or Read the error step by use of peripheral "CAN’T EXECUTE(P)"...
Page 374 Stop The CPU has checked if write and read Since this CPU hardware error, consult operations can be performed properly to Mitsubishi representative. the data memory area of CPU, and as a result, either or both has not been performed.
Page 375 Stop Interrupt occurs though no interrupt The hardware of a module is faulty. ERROR" module is installed. Replace the module and check the faulty module. Consult Mitsubishi representative. "SP. UNIT LAY. — Stop (1) Three or more computer link (1) Reduce the number of computer link ERROR."...
Page 376 Stop (1) The CPU walfunctioned due to (1) Take proper countermeasures for DOWN" noise. noise. (2) Hardware failure. (2) Consult Mitsubishi representative. "BATTERY — Continue (1) The battery voltage is low. (1) Replace the battery. ERROR" (2) The battery lead connector is not (2) Connect the lead connector to use connected.
Page 377: Error Code List For The Anacpu And A3A Board
ERROR CODE LIST Error Code List for the AnACPU and A3A Board Table 9.3 shows the error messages, error codes, description and cause of error and corrective actions of detailed error codes. Error codes, detailed error codes and error steps are stored in the following special registers.
Page 378 ERROR CODE LIST Table 9.3 Error Code List for AnACPU and A3A Board (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "PARAMETER STOP Capacity settings of the main and sub Read parameters in the CPU memory, ERROR"...
Page 379 ERROR CODE LIST Table 9.3 Error Code List for AnACPU and A3A Board (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "CAN'T STOP The same device number is used at two Eliminate the same pointer numbers EXECUTE (P)"...
Page 380 ERROR CODE LIST Table 9.3 Error Code List for AnACPU and A3A Board (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "CHK FORMAT STOP Instructions (including ) other than Check the program of the ERR."...
Page 381 Since this is CPU hardware error, execution of the (1) When the instruction was to consult Mitsubishi representative. be executed, the instruction was instruction.) read as other instruction code due to noise. (2) The instruction changed to other instruction code due to unknown cause.
Page 382 FROM TO made, consult Mitsubishi representative. is received. If parameter I/O assignment is being executed, no response is received from a special function module at initial communication.
Page 383 Though the interrupt module is not Since it is hardware error of a module, ERROR" loaded, an interrupt occurred. replace and check a defective module. For defective modules, consult Mitsubishi representative. "SP.UNIT STOP A special function module is assigned Execute I/O assignment again using LAY.ERR."...
Page 384 (3) If the same error indication is given device does not conform with the again, it is hardware failure. data of link parameters read by the Consult Mitsubishi representative. CPU. Or, link parameters are not written. (2) Total number of local stations is set at 0.
Page 385 ERROR CODE LIST Table 9.3 Error Code List for AnACPU and A3A Board (Continue) Detailed Error Error Error Massage Code Error and Cause Code States (D9008) (D9091) "OPERATION Stop or (1) An instruction which cannot be (1) Read the error step using a ERROR"...
Page 386: Error Code List For The Anucpu, A2Ascpu And A2Ush Board
ERROR CODE LIST Error Code List for the AnUCPU, A2ASCPU and A2USH board Table 9.4 shows the error messages, error codes, description and cause of error and corrective actions of detailed error codes. (*: The detailed error codes added to AnUCPU, A2ASCPU and A2USH board) Error codes, detailed error codes and error steps are stored in the following special registers.
Page 387 ERROR CODE LIST Table 9.4 Error Code List for the AnU, A2AS and A2USH board (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "PARAMETER STOP Capacity settings of the main and sub Read parameters in the CPU memory, ERROR"...
Page 388 ERROR CODE LIST Table 9.4 Error Code List for the AnU, A2AS and A2USH board (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "CAN'T STOP The same device number is used at two Eliminate the same pointer numbers EXECUTE (P)"...
Page 389 ERROR CODE LIST Table 9.4 Error Code List for the AnU, A2AS and A2USH board (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "CHK FORMAT STOP Instructions (including ) other than Check the program of the ERR."...
Page 390 Since this is CPU hardware error, execution of the (1) When the instruction was to consult Mitsubishi representative. be executed, the instruction was instruction.) read as other instruction code due to noise. (2) The instruction changed to other instruction code due to unknown cause.
Page 391 "I/O INT. — STOP Though the interrupt module is not Since it is hardware error of a module, ERROR" loaded, an interrupt occurred. replace and check a defective module. For defective modules, consult Mitsubishi representative. 9 - 25...
Page 392 ERROR CODE LIST Table 9.4 Error Code List for the AnU, A2AS and A2USH board (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "SP.UNIT STOP A special function module is assigned Execute I/O assignment again using LAY.ERR."...
Page 393 (4) Persistent error occurrence may written to the link parameter area indicate a hardware fault. Consult differs from the link parameter data your nearest Mitsubishi read by the CPU. Alternatively, no representative, explaining the nature link parameters have been written.
Page 394 (3) Persistent error occurrence may differ from the actual network indicate a hardware fault. Consult system. your nearest Mitsubishi (2) The link parameters for the first link representative, explaining the nature unit have not been written. of the problem.
Page 395 ERROR CODE LIST Table 9.4 Error Code List for the AnU, A2AS and A2USH board (Continue) Detailed Error Error Error Massage Code Error and Cause Code States (D9008) (D9091) "OPERATION Stop or (1) When file registers (R) are used, Read the error step using a peripheral ERROR"...
Page 396 ERROR CODE LIST Table 9.4 Error Code List for the AnU, A2AS and A2USH board (Continue) Detailed Error Error Error Massage Code Error and Cause Code States (D9008) (D9091) "OPERATION Stop or (1) An instruction which cannot be (1) Read the error step using a ERROR"...
Page 397: Error Code List For The Qcpu-A (A Mode)
ERROR CODE LIST Error Code List for the QCPU-A (A Mode) Meanings and causes of error message, error codes, detailed error codes and corrective actions are described. Table 9.5 Error Code List for the QCPU-A (A Mode) Detailed Error Error Error Massage Code Error and Cause...
Page 398 ERROR CODE LIST Table 9.5 Error Code List for the QCPU-A (A Mode) (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "PARAMETER STOP Either of settings of the remote RUN/ Read parameters in the CPU memory, ERROR"...
Page 399 ERROR CODE LIST Table 9.5 Error Code List for the QCPU-A (A Mode) (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "CHK FORMAT STOP Instructions (including ) other than Check the program of the ERR."...
Page 400 (1) Reset and run the CPU again. If the EXECUTE" capacity was executed without same error recurs, Since this is CPU (Checked at executing the instructions. hardware error, consult Mitsubishi execution of the (1) When the instruction was to be representative. executed, the instruction was read instruction.) as other instruction code due to noise.
Page 401 "I/O INT. — STOP Though the interrupt module is not Since it is hardware error of a module, ERROR" loaded, an interrupt occurred. replace and check a defective module. For defective modules, consult Mitsubishi representative. 9 - 35...
Page 402 ERROR CODE LIST Table 9.5 Error Code List for the QCPU-A (A Mode) (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "SP.UNIT STOP A special function module is assigned Execute I/O assignment again using LAY.ERR."...
Page 403 (4) Persistent error occurrence may written to the link parameter area indicate a hardware fault. Consult differs from the link parameter data your nearest Mitsubishi read by the CPU. Alternatively, no representative, explaining the nature link parameters have been written.
Page 404 (3) Persistent error occurrence may differ from the actual network indicate a hardware fault. Consult system. your nearest Mitsubishi (2) The link parameters for the second representative, explaining the nature link unit have not been written. of the problem.
Page 405 ERROR CODE LIST Table 9.5 Error Code List for the QCPU-A (A Mode) (Continue) Detailed Error Error Error Massage Code Error and Cause Corrective Action Code States (D9008) (D9091) "OPERATION Stop or (1) When the AD57(S1) or AD58 was AD57 (S1) and AD58 cannot be used ERROR"...
Page 406: Appendices
APPENDICES Appendix 1 LISTS OF SPECIAL RELAYS AND SPECIAL REGISTERS Appendix 1.1 List of Special Relays The special relays are the internal relays that have specific applications in the sequencer. Therefore, do not turn the special register ON/OFF on the program. (Except for the ones marked by *1 or *2 in the table.) Table 1.1 Special Relay List Number...
Page 407 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU • Clears the data memory including the latch range Data memory OFF: No processing (other than special relays and special registers) in Usable with all M9016 clear flag ON: Output clear remote run mode from computer, etc.
Page 408 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU 0.05 0.1 second M9030 seconds 0.05 clock seconds 0.2 second M9031 • 0.1 second, 0.2 second, 1 second, 2 second, and 1 seconds clock seconds minute clocks are generated. •...
Page 409 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU OFF:Except during Unusable with A1 M9046 Sampling trace trace • Switched on during sampling trace. and A1N. ON: During trace OFF:Sampling trace Sampling trace stop • Turn on M9047 to execute sampling trace. Unusable with A1 M9047 preparation...
Page 410 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU • Turned on when one of remote terminal modules has become a faulty station. (Communication error is detected when normal communication is not restored after the number of retries set at D9174.) Remote OFF:Normal...
Page 411 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU OFF:Reading time • Turn on to reduce the search time of A8UPU/ Time required reduction OFF A8PUJ. Usable with AnU for search of M9070 ON: Reading time (In this case, the scan time of the CPU module and A2US(H).
Page 412 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU • Compares the setting value at D9077 with the time elapsed from the start of measurement (accumulation time) at every scan. Then, performs the following operations: Setting value > Accumulation time: Turns M9077 ON and clears the accumulation Sequence time.
Page 413 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU OFF:Communication request to remote Registration Usable with AnA, terminal modules area busy signal • Indication of communication enable/disable to AnA, AnU, A2AS, enabled M9081 remote terminal modules connected to the MINI —...
Page 414 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU • After the head address of the required I/O module is set to D9094, switching M9094 on allows the I/O module to be changed in online mode. (One module is only allowed to be changed by one setting.) *2 *3...
Page 415 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU Usable with AnN*, • Selects consecutive or step-by-step transfer of AnA*, AnU, OFF:Consecutive step steps of which transfer conditions are established Consecutive A2AS, QCPU-A transfer disable when all of the transfer conditions of consecutive step transfer —...
Page 416 APPENDICES Table 1.1 Special Relay List (Continue) Number Name Description Details Applicable CPU Usable with AnN*, AnA*, AnU, Active step • Turned on when sampling trace of all specified A2AS, QCPU-A OFF:Trace start M9180 sampling trace blocks is completed. Turned off when sampling —...
Page 417 APPENDICES POINTS (1) Contents of the M special relays are all cleared by power off, latch clear or reset with the reset key switch. When the RUN/STOP key switch is set in the STOP position, the contents are retained. (2) The above relays with numbers marked *1 remain "on" if normal status is restored.
Page 418: Special Relays For Link
APPENDICES Appendix 1.2 Special Relays for Link The link special relays are internal relays which are switched on/off by various factors occurring during data link operation. Their ON/OFF status will change if an error occurs during normal operation. These special registers are applicable to all types of CPUs except the A3V. For description of the special registers for link for the A3V, refer to the A3VTS Data Link System User’s Manual.
Page 419 APPENDICES Table 1.2 Link Special Relay List (Continue) Number Name Description Details Local station OFF:RUN or STEP RUN mode Depends on whether or not a local station is in STOP or M9232 operating status ON: STOP or PAUSE mode PAUSE mode. Local station error OFF:No error Depends on whether or not a local station has detected an...
Page 420 APPENDICES Link special relays only valid when the host is a local station Table 1.3 Link Special Relay List Number Name Description Details LRDP instruction OFF:Incomplete On indicates that the LRDP instruction is complete at the M9204 complete ON: Complete local station.
Page 421: Special Registers
APPENDICES Appendix 1.3 Special Registers Special registers are data registers of which applications have been determined inside the PC. Therefore, do not write data to the special registers in the program (except the ones with numbers marked 2 in the table). Table 1.4 Special Register List Number Name...
Page 422 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU The number of bits • The number of bits detected by execution of the SUM SUM instruction Dedicated to D9003 detected by SUM instruction are stored. in BIN code and updated every —...
Page 423 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU • When operation error has occurred during execution of Step number at which application instruction, the step number, at which the Unusable with D9010 Error step operation error has error has occurred, is stored in BIN code.
Page 424 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU ROM/RAM • Indicates the setting of memory select chip. One value Usable with A1 — setting of 0 to 2 is stored in BIN code. and A1N. E 2 PROM Main program (ROM)
Page 425 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU • Stores the year (2 lower digits) and month in BCD....
Page 426 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU D9021 • Sets the head station number of remote terminal D9022 modules connected to A2C and A52G. Setting is not D9023 necessarily in the order of station numbers. D9024 A2CCPUC24:1 to 57 Other CPUs:1 to 61...
Page 427 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU • Designate the device number for the extension file register for direct read and write in 2 words at D9036 and D9037 in BIN data. D9036 Use consecutive numbers beginning with R0 of block No.
Page 428 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU • Stores the step number in which error 84 occurred in the SFC program in BIN code. Step number in which Usable with D9052 Error step Stores "0" when errors 80, 81 and 82 occurred. —...
Page 429 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU Stores the bit pattern of the base module in abnormal condition. When basic base module is abnormal: Bit 0 turns ON. When 1st expansion base module is abnormal: Bit 1 Stores the bit pattern turns ON.
Page 430 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU Sequence • Stores the accumulation time used by M9077. Dedicated to accumulation Accumulation time Setting range: 1 to 255ms (Default: 5ms) D9077 — QCPU-A time setting * When the value other than 1 to 255 ms is designated, (A Mode).
Page 431 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU Usable with AnN*, AnA*, Detail error number of SFC program AnU, A2US(H), the error which • Stores the detail error number of the error occurred in a D9091 detail error —...
Page 432 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU • Output module numbers (in units of 16 points), of which D9100 fuses have blown, are entered in bit pattern. (Preset output unit numbers when parameter setting has been performed.) D9101 15 14...
Page 433 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU • When I/O modules, of which data are different from D9116 those entered at power-on, have been detected, the I/ O unit numbers (in units of 16 points) are entered in bit pattern.
Page 434 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU • When one of F0 to 255 (F0 to 2047 for AnA and AnU) is turned on by , F number, which has turned on, D9125 SET F is entered into D9125 to D9132 in due order in BIN code.
Page 435 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU D9141 D9142 D9143 D9144 D9145 D9146 • Stores the number of retries executed to I/O modules or remote terminal modules which caused D9147 communication error. D9148 (Retry processing is executed the number of times set at D9174.) D9149 •...
Page 436 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Applicable CPU Mode setting Auto- • When an I/O module or a remote matic terminal module caused communication online error, the station is placed offline. return • Communication with normal stations is enabled continued.
Page 437 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details Limit switch output state Dedicated to D9180 — torage areas for A73. • Stores output state of limit switch function. axes 1 and 2 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Limit switch D9180 Y0E Y0D Y0C Y0B Y0A Y09 Y08 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00...
Page 438 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details • Stores error code when the manual pulse generator axis setting error flag (M9077) is turned on in the bit each corresponds to each axis number. b8 b7 axis axis axis axis...
Page 439 APPENDICES Table 1.4 Special Register List (Continue) Number Name Description Details • Bit which corresponds to faulty I/O module or remote terminal module is set (1). D9196 (Bit which corresponds to a faulty station is set when normal communication cannot be restored after executing the number of retries set at D9174.) •...
Page 440: Special Registers For Link
APPENDICES Appendix 1.4 Special registers for Link The link special register stores the result of any error, etc. which may occur during data communication as a numeric value. By monitoring the link special register, any station number with an error or fault diagnosis can be read.
Page 441 APPENDICES Table 1.5 Link special Register (Continue) Number Name Description Details • Loopback in forward loop only Master station Station 1 Station 2 Station 3 Station n Forward loopback D9204 Link status • Loopback in reverse loop only (Continue) Master station Station 1 Station 2...
Page 442 APPENDICES Table 1.5 Link special Register (Continue) Number Name Description Details Stores the local station numbers which are in STOP or PAUSE Local station Stores the status of mode. D9212 operating status stations 1 to 16 Device number b15 b14 b13 b12 b11 b10 Local station Stores the status of D9213...
Page 443 APPENDICES Table 1.5 Link special Register (Continue) Number Name Description Details Initial communication Stores the local or remote station numbers while they are Stores the status of D9224 between local or communicating the initial data with their relevant master station. stations 1 to 16 remote I/O stations Device...
Page 444 APPENDICES Link special registers only valid when the host station is a local station Table 1.6 Link Special Register List Number Name Description Details Own station number Stores a station number. D9243 Allows a local station to confirm its own station number. check (0 to 64) Total number of slave...
Page 445: Appendix 2 Operation Processing Time
APPENDICES MELSEC-A APPENDIX 2 OPERATION PROCESSING TIME The operation processing time of each instruction is shown in the tables on the following pages. The operation processing time differs depending on values in the source and destination. Use the values in the tables as a guide to processing time. (1) Processing time varies depending on the I/O control mode used with any instruction operating on inputs or ontputs.
Page 446 APPENDICES MELSEC-A (3) The following processings may take a slightly longer period of time. (a) Device specified indirectly as source or destination is used with the index register (V, Z) . Example: K400 D10Z Index qualification (b) The number of digits specified for the devices used with any basic or application instruction is not K4 or K8 and/or the device number specified is not 0 or a multiple of 8 (0 or a multiple of 16 when the A3H, A3M, AnA, A2AS, AnU or QCPU-A (A Mode) is used) .
Page 447: Instruction Processing Time Of Small Size, Compact Cpus
APPENDICES MELSEC-A Appendix 2.1 Instruction Processing Time of Small Size, Compact CPUs (1) Sequence instructions Table 2.1 Instruction Processing Time of Small Size, Compact CPUs Processing Time (µs) Instruction Condition (Device) A1SJH/A1SH A2SH (S1) LD, LDI, 0.33 0.25 AND, ANI, Y, M, L, B, F, T, C 0.33 0.33...
Page 448 APPENDICES MELSEC-A Table 2.1 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS Instruction Condition (Device) A52G A0J2H A1FX A2USH (S1) board LD, LDI, 0.20 0.09 0.25 AND, ANI, Y, M, L, B, F, T, C 0.20 0.09 0.25...
Page 449 APPENDICES MELSEC-A Table 2.1 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) Instruction Condition (Device) A1SJH/A1SH A2SH (S1) Unexecuted 0.33 0.32 Unchanged 0.33 0.32 (OFF → OFF) Executed Changed (ON → OFF) 0.33 0.32 Unexecuted 0.33 0.33 0.32 0.25...
Page 450 APPENDICES MELSEC-A Table 2.1 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS Instruction Condition (Device) A52G A0J2H A1FX A2USH (S1) board Unexecuted 0.40 0.17 0.32 Unchanged 0.40 0.17 0.32 (OFF → OFF) Executed Changed (ON → OFF) 0.40 0.17 0.32...
Page 451 APPENDICES MELSEC-A Table 2.1 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) Instruction Condition (Device) A1SJH/A1SH A2SH (S1) Unexecuted 16.8 16.8 11.7 13.7 17.2 17.2 11.6 13.7 Executed 17.2 17.2 11.7 13.7 Unexecuted 15.2 15.2 11.7 11.7 M, L, B, F 15.6...
Page 452 APPENDICES MELSEC-A Table 2.1 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS Instruction Condition (Device) A52G A0J2H A1FX A2USH (S1) board Unexecuted 0.99 11.7 0.99 11.6 Executed 0.99 11.7 Unexecuted 0.99 11.7 M, L, B, F 0.99 11.6 Executed...
Page 453 APPENDICES MELSEC-A POINTS (1) "When not executed" in the above table indicates that the input condition is off. Input condition (2) "When not counted" of OUT C instruction indicates that the input condition remains on and the counter does not count. (3) "OFF"...
Page 454 APPENDICES MELSEC-A (2) Basic Instructions Table 2.2 Instruction Processing Time of Small Size, Compact CPUs Processing Time (µs) A1SJH/A1SH A2SH (S1) Instruction Condition Direct Mode Refresh Refresh Direct Refresh Direct Other than Mode Mode Mode Mode Mode X, Y X, Y 19.2 19.6 14.7...
Page 455 APPENDICES MELSEC-A Table 2.2 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS (S1) A2USH A52G A0J2H A1FX board Instruction Condition Direct Mode Refresh Refresh Refresh Refresh Refresh Refresh Other Mode Mode Mode Mode Mode Mode X, Y than X, Y...
Page 456 APPENDICES MELSEC-A Table 2.2 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A1SJH/A1SH A2SH (S1) Instruction Condition Direct Mode Refresh Refresh Direct Refresh Direct Other than Mode Mode Mode Mode Mode X, Y X, Y + S D 11.6 11.9 +P S D...
Page 457 APPENDICES MELSEC-A Table 2.2 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS (S1) A52G A0J2H A1FX A2USH board Instruction Condition Direct Mode Refresh Refresh Refresh Refresh Refresh Refresh Other Mode Mode Mode Mode Mode Mode X, Y than X, Y...
Page 458 APPENDICES MELSEC-A Table 2.2 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A1SJH/A1SH A2SH (S1) Instruction Condition Direct Mode Refresh Refresh Direct Refresh Direct Other than Mode Mode Mode Mode Mode X, Y X, Y B+ S D 33.6 34.1 25.3...
Page 459 APPENDICES MELSEC-A Table 2.2 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS (S1) A52G A0J2H A1FX A2USH board Instruction Condition Direct Mode Refresh Refresh Refresh Refresh Refresh Refresh Other Mode Mode Mode Mode Mode Mode X, Y than X, Y...
Page 460 APPENDICES MELSEC-A Table 2.2 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A1SJH/A1SH A2SH (S1) Instruction Condition Direct Mode Refresh Refresh Direct Refresh Direct Other than Mode Mode Mode Mode Mode X, Y X, Y 11.8 12.3 MOVP 11.8...
Page 461 APPENDICES MELSEC-A Table 2.2 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS (S1) A52G A0J2H A1FX A2USH board Instruction Condition Direct Mode Refresh Refresh Refresh Refresh Refresh Refresh Other Mode Mode Mode Mode Mode Mode X, Y than X, Y...
Page 462 APPENDICES MELSEC-A (3) Application Instructions Table 2.3 Instruction Processing Time of Small Size, Compact CPUs Processing Time (µs) A1SJH/A1SH A2SH (S1) Instruction Condition Direct Mode Refresh Refresh Direct Refresh Direct Other than Mode Mode Mode Mode Mode X, Y X, Y WAND S D 15.4 15.7...
Page 463 APPENDICES MELSEC-A Table 2.3 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS (S1) A52G A0J2H A1FX A2USH board Instruction Condition Direct Mode Refresh Refresh Refresh Refresh Refresh Refresh Other Mode Mode Mode Mode Mode Mode X, Y than X, Y...
Page 464 APPENDICES MELSEC-A Table 2.3 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A1SJH/A1SH A2SH (S1) Instruction Condition Direct Mode Refresh Refresh Direct Refresh Direct Other than Mode Mode Mode Mode Mode X, Y X, Y ROL n 13.2 13.7 10.0...
Page 465 APPENDICES MELSEC-A Table 2.3 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS (S1) A52G A0J2H A1FX A2USH board Instruction Condition Direct Mode Refresh Refresh Refresh Refresh Refresh Refresh Other Mode Mode Mode Mode Mode Mode X, Y than X, Y...
Page 466 APPENDICES MELSEC-A Table 2.3 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A1SJH/A1SH A2SH (S1) Instruction Condition Direct Mode Refresh Refresh Direct Refresh Direct Other than Mode Mode Mode Mode Mode X, Y X, Y ENCO S D n 92.6 93.1 69.5...
Page 467 APPENDICES MELSEC-A Table 2.3 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS (S1) A52G A0J2H A1FX A2USH board Instruction Condition Direct Mode Refresh Refresh Refresh Refresh Refresh Refresh Other Mode Mode Mode Mode Mode Mode X, Y than X, Y...
Page 468 APPENDICES MELSEC-A Table 2.3 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A1SJH/A1SH A2SH (S1) Instruction Condition Direct Mode Refresh Refresh Direct Refresh Direct Other than Mode Mode Mode Mode Mode X, Y X, Y Only device 8448 8448...
Page 469 APPENDICES MELSEC-A Table 2.3 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS (S1) A52G A0J2H A1FX A2USH board Instruction Condition Direct Mode Refresh Refresh Refresh Refresh Refresh Refresh Other Mode Mode Mode Mode Mode Mode X, Y than X, Y...
Page 470 APPENDICES MELSEC-A Table 2.3 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A1SJH/A1SH A2SH (S1) Direct Mode Direct Mode Direct Mode Instruction Condition Refresh Mode Refresh Mode Refresh Mode Other than Other than Other than X, Y X, Y X, Y X, Y...
Page 471 APPENDICES MELSEC-A Table 2.3 Instruction Processing Time of Small Size, Compact CPUs (Continue) Processing Time (µs) A2USH-S1 A2AS (S1) A52G A0J2H A1FX A2USH board Instruction Condition Refresh Refresh Refresh Refresh Direct Mode Mode Mode Mode Mode Refresh Refresh Refresh Mode Mode Mode Other...
Page 472 APPENDICES MELSEC-A POINTS (1) All the application instructions indicated above are used without index qualification. (2) When unexecuted, any instruction is processed during the following time: An, A2C and A0J2H........(Number of steps+1) x 1.25 (µs) AnN, AnS, A3V, A73 and A3N board ..(Number of steps+1) x 1.0 (µs) A1SH, A1SJH ...........(Number of steps+1) x 0.33 (µs) A2SH (S1), A1FX........(Number of steps+1) x 0.25 (µs) A3H, A3M..........(Number of steps+1) x 0.2 (µs)
Page 473: Instruction Processing Time Of Cpus
APPENDICES MELSEC-A Appendix 2.2 Instruction Processing Time of CPUs (1) Sequence instructions Table 2.4 Instruction Processing Time of CPUs Processing Time (µs) A3A, AnN, A3V, A73, A2A, Instruction Condition (Device) A3H, A3M A3U, A3N Board LD, LDI 0.20 0.20 0.15 AND, ANI Y, M, L, B, F, T, C 0.20...
Page 474 APPENDICES MELSEC-A Table 2.4 Instruction Processing Time of CPUs (Continue) Processing Time (µs) A3A, AnN, A3V, A73, A2A, Instruction Condition (Device) A3H, A3M A3U, A3N Board Unexecuted 0.35 0.35 0.40 0.30 Unchanged (ON → ON) 0.35 0.35 0.40 0.30 Executed Changed (OFF →...
Page 475 APPENDICES MELSEC-A Table 2.4 Instruction Processing Time of CPUs (Continue) Processing Time (µs) A3A, AnN, A3V, A73, A2A, Instruction Condition (Device) A3H, A3M A3U, A3N Board Unexecuted 0.80 0.80 Executed SFTP Unexecuted 0.80 0.80 M, L B, F Executed  0.20 0.20 0.20...
Page 476 APPENDICES MELSEC-A POINTS (1) "When not executed" in the above table indicates that the input condition is off. Input condition (2) "When not counted" of OUT C instruction indicates that the input condition remains on and the counter does not count. (3) "OFF"...
Page 477 APPENDICES MELSEC-A (2) Basic instruction Table 2.5 Instruction Processing Time of CPUs Processing Time (µs) AnN, A3V, A73 A3A, A3H, A3M A2A, A2U A3U, A4U A3N board Instruction Condition Other Other X, Y X, Y than X, Y than X, Y AND= LDD= 157*...
Page 478 APPENDICES MELSEC-A Table 2.5 Instruction Processing Time of CPUs (Continue) Processing Time (µs) AnN, A3V, A73 A3A, A3H, A3M A2A, A2U A3U, A4U A3N board Instruction Condition Other Other X, Y X, Y than X, Y than X, Y + S D + P S D D+ S D D+P S D...
Page 479 APPENDICES MELSEC-A Table 2.5 Instruction Processing Time of CPUs (Continue) Processing Time (µs) AnN, A3V, A73 A3A, A3H, A3M A2A, A2U A3U, A4U A3N board Instruction Condition Other Other X, Y X, Y than X, Y than X, Y DB+P S1 S2 D 274* 274* 308*...
Page 480 APPENDICES MELSEC-A Table 2.5 Instruction Processing Time of CPUs (Continue) Processing Time (µs) AnN, A3V, A73 A3A, A3H, A3M A2A, A2U A3U, A4U A3N board Instruction Condition Other Other X, Y X, Y than X, Y than X, Y BMOVP S D n n=96 7498 7144...
Page 481 APPENDICES MELSEC-A (3) Application instructions Table 2.6 Instruction Processing Time of CPUs Processing Time (µs) AnN, A3V, A73 A3H, A3M A2A, A2U A3N Board A3U, A4U Instruction Condition Other Other than X, Y than X, Y X, Y X, Y WAND S D WANDP S D DAND...
Page 482 APPENDICES MELSEC-A Table 2.6 Instruction Processing Time of CPUs (Continue) Processing Time (µs) AnN, A3V, A73 A3H, A3M A2A, A2U A3N Board A3U, A4U Instruction Condition Other Other than X, Y than X, Y X, Y X, Y ROL n ROLP n RCL n RCLP n...
Page 483 APPENDICES MELSEC-A Table 2.6 Instruction Processing Time of CPUs (Continue) Processing Time (µs) AnN, A3V, A73 A3H, A3M A2A, A2U A3N Board A3U, A4U Instruction Condition Other Other than X, Y than X, Y X, Y X, Y DECO S D n 200* 200* 205*...
Page 484 APPENDICES MELSEC-A Table 2.6 Instruction Processing Time of CPUs (Continue) Processing Time (µs) AnN, A3V, A73 A3H, A3M A2A, A2U A3N Board A3U, A4U Instruction Condition Other Other than X, Y than X, Y X, Y X, Y Only  device 8448 8448...
Page 485 APPENDICES MELSEC-A Table 2.6 Instruction Processing Time of CPUs (Continue) Processing Time (µs) AnN, A73 A3A, A2A, A2U A3N Board A3U, A4U Condi- Instruction D, R D, R tion Other Other Other Other D, R than X, Y than X, Y than X, Y than...
Page 486: List Of Instruction Processing Time Of Qcpu-A (A Mode)
APPENDICES MELSEC-A Appendix 2.3 List of Instruction Processing Time of QCPU-A (A Mode) The following table shows the instruction processing time of QCPU-A (A mode). (1) Sequence instructions Table 2.7 Instruction Processing Time of QCPU-A (A Mode) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A...
Page 487 APPENDICES MELSEC-A Table 2.7 Instruction Processing Time of QCPU-A (A Mode) (Continue) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A QnHCPU-A Special M At no execution 0.316 0.136 At execution 0.316 0.136 At no execution 0.798 0.343 At execution 35.1 15.1 At no execution 0.158...
Page 488 APPENDICES MELSEC-A Table 2.7 Instruction Processing Time of QCPU-A (A Mode) (Continue) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A QnHCPU-A At no execution 0.561 0.242 At execution 1.75 0.755 SFTP At no execution 0.561 0.242 M, L, B, F At execution 1.75 0.755...
Page 489 APPENDICES MELSEC-A (2) Basic instructions Table 2.8 Instruction Processing Time of QCPU-A (A Mode) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A QnHCPU-A 1.67 0.721 AND= 1.27 0.546 1.76 0.758 LDD= 4.50 1.94 ANDD= 3.48 1.50 ORD= 4.43 1.91 LD<> 1.92 0.829 AND<>...
Page 490 APPENDICES MELSEC-A Table 2.8 Instruction Processing Time of QCPU-A (A Mode) (Continue) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A QnHCPU-A + S D 1.11 0.480 +P S D 1.11 0.480 D+ S D 1.60 0.688 D+P S D 1.60 0.688 + S1 S2 D 1.27...
Page 491 APPENDICES MELSEC-A Table 2.8 Instruction Processing Time of QCPU-A (A Mode) (Continue) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A QnHCPU-A B- S D 2.47 1.07 B-P S D 2.47 1.07 DB- S D 12.7 5.48 DB-P S D 12.7 5.48 B- S1 S2 D 5.58...
Page 492 APPENDICES MELSEC-A POINTS (1) All the basic instructions indicated above are used without index qualification. (2) When unexecuted, any instruction is processed during the following time: Q02CPU-A .........(Number of steps + 1) × 0.079 (µs) Q02HCPU-A, Q06HCPU-A ....(Number of steps + 1) × 0.034 (µs) APP −...
Page 493 APPENDICES MELSEC-A (3) Application instructions Table 2.9 Instruction Processing Time of QCPU-A (A Mode) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A QnHCPU-A WAND S D 1.11 0.480 WANDP S D 1.11 0.480 DAND 5.18 2.23 DANDP 5.18 2.23 WAND S1 S2 D 3.03 1.30 WANDP S1 S2 D...
Page 494 APPENDICES MELSEC-A Table 2.9 Instruction Processing Time of QCPU-A (A Mode) (Continue) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A QnHCPU-A ROR n 2.31 0.997 RORP n 2.31 0.997 RCR n 2.55 1.10 RCRP n 2.55 1.10 ROL n 2.31 0.997 ROLP n 2.31...
Page 495 APPENDICES MELSEC-A Table 2.9 Instruction Processing Time of QCPU-A (A Mode) (Continue) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A QnHCPU-A 5.98 2.58 SUMP 5.98 2.58 DSUM 13.6 5.59 DSUMP 13.6 5.59 DECO S D n 11.1 4.80 DECOP S D n 11.1 4.80 2.55...
Page 496 APPENDICES MELSEC-A Table 2.9 Instruction Processing Time of QCPU-A (A Mode) (Continue) Instruction Processing Time (µs) Instruction Condition (Device) QnCPU-A QnHCPU-A 1.99 0.858 WDTP 1.99 0.858 When the number of conditional contacts is 1 13.2 5.67 When the number of conditional contacts is 50 When the number of conditional contacts is 100 When the number of conditional contacts is 150 1495...
Page 497: Appendix 3 Ascii Code Table
APPENDICES MELSEC-A APPENDIX 3 ASCII CODE TABLE Bit number b Column Line ) DLE ’ ) SOH ) STX " ) ETX ) EOT ) ENQ ) NAK ) ACK ) SYN & ) ETB ’ (BS) (HT) (LF/NL) (VT) (FF) (FS) <...
Page 498: Appendix 4 Formats Of Program Sheets
APPENDICES MELSEC-A APPENDIX 4 FORMATS OF PROGRAM SHEETS Sheet format 1-1 16 points occupying module 32 points occupying module 64 points occupying module APP − 93...
Page 499 APPENDICES MELSEC-A Sheet format 1-2 16 points occupying module 32 points occupying module 64 points occupying module APP − 94...
Page 500 APPENDICES MELSEC-A Sheet format 1-3 CHECKED PREPARED SHEET NO. MELSEC-A CODING SHEET Step Number Instruction Device Remarks APP − 95...
Page 501 APPENDICES MELSEC-A Sheet format 1-4 CHECKED PREPARED SHEET NO. MELSEC-A BIT DEVICE LIST Signal Description Signal Description APP − 96...
Page 502 APPENDICES MELSEC-A Sheet format 1-5 SHEET NO. CHECKED PREPARED MELSEC-A WORD DEVICE LIST Data Data Description Description (16 bits/data) (16 bits/data) APP − 97...
Page 503 APPENDICES MELSEC-A Sheet format 1-6 SHEET NO. CHECKED PREPARED MELSEC-A ANNUNCIATOR LIST Failure Type, Condition → Troubleshooting Point Failure External Failure Name Memory Number APP − 98...
Page 504 APPENDICES MELSEC-A Sheet format 1-7 SHEET NO. CHECKED PREPARED MELSEC-A TIMER, COUNTER LIST Number Set Value K Description Application, Operation (Count Input), etc. APP − 99...
Page 505 APPENDICES MELSEC-A MEMO APP − 100...
Page 506 6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from Mitsubishi. 7. Any other failure found not to be the responsibility of Mitsubishi or that admitted not to be so by the user. 2. Onerous repair term after discontinuation of production (1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is discontinued.

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Mitsubishi MELSEC-A Series Programming Manual

1 Introduction

2 Instructions

3 Instruction Structure

4 Instruction Format

5 Sequence Instructions

6 Basic Instructions

7 Application Instructions

8 Microcomputer Mode

9 Error Code List

Appendices

Appendix 1 Lists of Special Relays and Special Registers

Appendix 1.1 List of Special Relays

Appendix 1.2 Special Relays for Link

Appendix 1.3 Special Registers

Appendix 1.4 Special Registers for Link

Appendix 2 Operation Processing Time

Appendix 2.1 Instruction Processing Time of Small Size, Compact Cpus

Appendix 2.2 Instruction Processing Time of Cpus

Appendix 2.3 List of Instruction Processing Time of QCPU-A (a Mode)

Appendix 3 Ascii Code Table

Appendix 4 Formats of Program Sheets

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Summary of Contents for Mitsubishi MELSEC-A Series