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Motorola MPC8260 PowerQUICC II User Manual

Motorola processor users manual
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MPC8260UM/D
4/1999
Rev. 0
ª
MPC8260 PowerQUICC II
UserÕs Manual
ª

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Summary of Contents for Motorola MPC8260 PowerQUICC II

  • Page 1 MPC8260UM/D 4/1999 Rev. 0 ª MPC8260 PowerQUICC II UserÕs Manual ª...
  • Page 2 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
  • Page 3 PowerPC Processor Core System Interface Unit (SIU) Clocks and Power Control Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Communications Processor Module Overview Serial Interface with Time-Slot Assigner Baud-Rate Generators (BRGs) SDMA Channels and IDMA Emulation Serial Communications Controllers (SCCs) SCC Transparent Mode SCC AppleTalk Mode Serial Management Controllers (SMCs)
  • Page 4 Overview PowerPC Processor Core Memory Map System Interface Unit (SIU) Reset External Signals 60x Signals The 60x Bus Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Communications Processor Module Overview Serial Interface with Time-Slot Assigner CPM Multiplexing Baud-Rate Generators (BRGs) Timers...

  • Page 5: Table Of Contents

    System Interface Unit (SIU) ... 1-6 1.2.3 Communications Processor Module (CPM) ... 1-6 Software Compatibility Issues ... 1-7 1.3.1 Signals... 1-7 Differences between MPC860 and MPC8260... 1-9 Serial Protocol Table... 1-9 MPC8260 Configurations ... 1-10 1.6.1 Pin Configurations ... 1-10 1.6.2 Serial Performance...
  • Page 6 Processor Version Register (PVR) ...2-16 2.3.2 PowerPC Instruction Set and Addressing Modes...2-16 2.3.2.1 Calculating Effective Addresses ...2-16 2.3.2.2 PowerPC Instruction Set ...2-16 2.3.2.3 MPC8260 Implementation-Specific Instruction Set ...2-18 Cache Implementation...2-18 2.4.1 PowerPC Cache Model...2-18 2.4.2 MPC8260 Implementation-Specific Cache Implementation...2-19 2.4.2.1 Data Cache ...2-19 2.4.2.2...
  • Page 7 Exception Priorities...2-26 Memory Management ...2-26 2.6.1 PowerPC MMU Model ...2-27 2.6.2 MPC8260 Implementation-Specific MMU Features ...2-28 Instruction Timing...2-29 Differences between the MPC8260Õs Core and the PowerPC 603e Microprocessor...2-30 System Configuration and Protection ...4-2 4.1.1 Bus Monitor ...4-3 4.1.2 Timers Clock...4-4 4.1.3...
  • Page 8 Hard Reset Configuration Word...5-8 5.4.2 Hard Reset Configuration Examples ...5-9 5.4.2.1 Single MPC8260 with Default Configuration...5-9 5.4.2.2 Single MPC8260 Configured from Boot EPROM...5-10 5.4.2.3 Multiple MPC8260s Configured from Boot EPROM...5-10 5.4.2.4 Multiple MPC8260s in a System with No EPROM...5-12 viii...
  • Page 9 Global (GBL)ÑInput...7-9 7.2.4.5 Caching-Inhibited (CI)ÑOutput...7-9 7.2.4.6 Write-Through (WT)ÑOutput ...7-9 7.2.5 Address Transfer Termination Signals...7-10 7.2.5.1 Address Acknowledge (AACK) ...7-10 7.2.5.1.1 Address Acknowledge (AACK)ÑOutput ...7-10 7.2.5.1.2 Address Acknowledge (AACK)ÑInput...7-10 MOTOROLA CONTENTS Title External Signals Chapter 7 60x Signals Contents Page Number...
  • Page 10 Arbitration Phase ...8-5 8.3.2 Address Pipelining and Split-Bus Transactions ...8-7 Address Tenure Operations ...8-7 8.4.1 Address Arbitration ...8-7 8.4.2 Address Pipelining...8-9 8.4.3 Address Transfer Attribute Signals ...8-10 CONTENTS Title Chapter 8 The 60x Bus MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 11 Clock Configuration...9-2 External Clock Inputs...9-5 Main PLL ...9-5 9.4.1 PLL Block Diagram ...9-5 9.4.2 Skew Elimination ...9-6 Clock Dividers...9-6 The MPC8260Õs Internal Clock Signals...9-6 9.6.1 General System Clocks ...9-7 PLL Pins...9-7 MOTOROLA CONTENTS Title Chapter 9 Clocks and Power Control...
  • Page 12 10.4 SDRAM Machine ...10-33 10.4.1 Supported SDRAM Configurations ...10-35 10.4.2 SDRAM Power-On Initialization ...10-35 10.4.3 JEDEC-Standard SDRAM Interface Commands...10-35 10.4.4 Page-Mode Support and Pipeline Accesses ...10-36 CONTENTS Title Chapter 10 Memory Controller MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 13 10.5.1.6 Extended Hold Time on Read Accesses ...10-57 10.5.2 External Access Termination ...10-60 10.5.3 Boot Chip-Select Operation ...10-61 10.5.4 Differences between MPC8xxÕs GPCM and MPC8260Õs GPCM...10-62 10.6 User-Programmable Machines (UPMs) ...10-62 10.6.1 Requests ...10-64 10.6.1.1 Memory Access Requests ...10-65 10.6.1.2 UPM Refresh Timer Requests ...10-65...
  • Page 14 The Wait Mechanism ...10-78 10.6.4.6 Extended Hold Time on Read Accesses ...10-79 10.6.5 UPM DRAM Configuration Example...10-79 10.6.6 Differences between MPC8xx UPM and MPC8260 UPM ...10-80 10.7 Memory System Interface Example Using UPM ...10-81 10.7.0.1 EDO Interface Example ...10-92 10.8 Handling Devices with Slow or Variable Access Times...10-100...
  • Page 15 Number 12.5 MPC8260 Restrictions ...12-30 12.6 Nonscan Chain Operation ...12-30 Communications Processor Module Overview 13.1 Features ...13-1 13.2 MPC8260 Serial Configurations ...13-3 13.3 Communications Processor (CP) ...13-4 13.3.1 Features ...13-4 13.3.2 CP Block Diagram ...13-4 13.3.3 PowerPC Core Interface...13-6 13.3.4 Peripheral Interface ...13-6...
  • Page 16 CMX SI2 Clock Route Register (CMXSI2CR) ...15-11 15.4.4 CMX FCC Clock Route Register (CMXFCR)...15-12 15.4.5 CMX SCC Clock Route Register (CMXSCR)...15-14 15.4.6 CMX SMC Clock Route Register (CMXSMR)...15-17 CONTENTS Title Chapter 14 Chapter 15 CPM Multiplexing MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 17 Peripheral to Memory ...18-10 18.5.2.1.2 Memory to Peripheral ...18-10 18.5.2.2 Single Address (Fly-By) Transfers ...18-11 18.5.2.2.1 Peripheral-to-Memory Fly-By Transfers ...18-11 18.5.2.2.2 Memory-to-Peripheral Fly-By Transfers ...18-11 MOTOROLA CONTENTS Title Chapter 16 Baud-Rate Generators (BRGs) Chapter 17 Timers Chapter 18 Contents Page...
  • Page 18 Function Code Registers (RFCR and TFCR)...19-15 19.3.3 Handling SCC Interrupts ...19-16 19.3.4 Initializing the SCCs...19-17 19.3.5 Controlling SCC Timing with RTS, CTS, and CD ...19-18 19.3.5.1 Synchronous Protocols ...19-18 xviii CONTENTS Title Chapter 19 MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 19 SCC UART Transmit Buffer Descriptor (TxBD) ...20-18 20.19 SCC UART Event Register (SCCE) and Mask Register (SCCM) ...20-19 20.20 SCC UART Status Register (SCCS)...20-21 20.21 SCC UART Programming Example ...20-22 20.22 S-Records Loader Application ...20-23 MOTOROLA CONTENTS Title Chapter 20 SCC UART Mode Contents Page Number...
  • Page 20 22.9 Sending and Receiving the Synchronization Sequence...22-9 22.10 Handling Errors in the SCC BISYNC ...22-9 22.11 BISYNC Mode Register (PSMR)...22-10 CONTENTS Title Chapter 21 SCC HDLC Mode Chapter 22 SCC BISYNC Mode MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 21 SCC Status Register in Transparent Mode (SCCS) ...23-13 23.14 SCC2 Transparent Programming Example ...23-13 24.1 Ethernet on the MPC8260 ...24-2 24.2 Features ...24-3 24.3 Connecting the MPC8260 to Ethernet ...24-4 24.4 SCC Ethernet Channel Frame Transmission...24-5 24.5 SCC Ethernet Channel Frame Reception ...24-6 MOTOROLA CONTENTS Title...
  • Page 22 SMC Function Code Registers (RFCR/TFCR) ...26-8 26.2.4 Disabling SMCs On-the-Fly...26-9 26.2.4.1 SMC Transmitter Full Sequence ...26-9 26.2.4.2 SMC Transmitter Shortcut Sequence ...26-9 26.2.4.3 SMC Receiver Full Sequence...26-9 xxii CONTENTS Title Chapter 25 SCC AppleTalk Mode Chapter 26 MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 23 SMC GCI Monitor Channel RxBD...26-32 26.5.6 SMC GCI Monitor Channel TxBD ...26-32 26.5.7 SMC GCI C/I Channel RxBD...26-33 26.5.8 SMC GCI C/I Channel TxBD ...26-33 26.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM) ...26-34 MOTOROLA CONTENTS Title Contents Page Number xxiii...
  • Page 24 FCC Parameter RAM ...28-10 28.7.1 FCC Function Code Registers (FCRx)...28-13 28.8 Interrupts from the FCCs...28-13 28.8.1 FCC Event Registers (FCCEx)...28-14 28.8.2 FCC Mask Registers (FCCMx) ...28-14 xxiv CONTENTS Title Chapter 27 Chapter 28 MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 25 Peak and Sustain Traffic Type (VBR) ...29-12 29.3.5.3.1 Example for Using VBR Traffic Parameters ...29-12 29.3.5.3.2 Handling the Cell Loss Priority (CLP)ÑVBR Type 1 and 2 ...29-13 29.3.5.4 Peak and Minimum Cell Rate Traffic Type (UBR+)...29-13 MOTOROLA CONTENTS Title Chapter 29 ATM Controller Contents Page...
  • Page 26 CAS Support...29-36 29.9.7 Trunk Condition ...29-37 29.9.8 ATM-to-ATM Data Forwarding ...29-37 29.10 ATM Memory Structure...29-37 29.10.1 Parameter RAM...29-37 29.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only) ...29-40 29.10.1.2 VCI Filtering (VCIF)...29-40 xxvi CONTENTS Title MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 27 AAL1 Sequence Number (SN) Protection Table (AAL1 Only) ...29-78 29.10.7 UNI Statistics Table ...29-78 29.11 ATM Exceptions ...29-79 29.11.1 Interrupt Queues...29-79 29.11.2 Interrupt Queue Entry ...29-80 29.11.3 Interrupt Queue Parameter Tables ...29-81 29.12 The UTOPIA Interface...29-82 MOTOROLA CONTENTS Title Contents Page Number xxvii...
  • Page 28 29.16.2 APC Configuration...29-93 29.16.3 Buffer Configuration ...29-93 30.1 Fast Ethernet on the MPC8260...30-2 30.2 Features...30-3 30.3 Connecting the MPC8260 to Fast Ethernet ...30-4 30.4 Ethernet Channel Frame Transmission...30-5 30.5 Ethernet Channel Frame Reception...30-7 30.6 Flow Control...30-8 30.7 CAM Interface...30-8 30.8 Ethernet Parameter RAM ...30-9...
  • Page 29 33.4 Programming the SPI Registers ...33-6 33.4.1 SPI Mode Register (SPMODE) ...33-6 33.4.1.1 SPI Examples with Different SPMODE[LEN] Values...33-8 33.4.2 SPI Event/Mask Registers (SPIE/SPIM) ...33-9 MOTOROLA CONTENTS Title Chapter 31 FCC HDLC Controller Chapter 32 FCC Transparent Controller Chapter 33...
  • Page 30 34.7.1.2 C Transmit Buffer Descriptor (TxBD)...34-14 35.1 Features...35-1 35.2 Port Registers...35-2 35.2.1 Port Open-Drain Registers (PODRAÐPODRD)...35-2 35.2.2 Port Data Registers (PDATAÐPDATD)...35-2 CONTENTS Title Chapter 34 C Controller Chapter 35 Parallel I/O Ports MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 31 35.4.2 Dedicated Pins...35-7 35.5 Ports Tables ...35-7 35.6 Interrupts from Port C ...35-19 Register Quick Reference Guide PowerPC RegistersÑUser Registers ... A-1 PowerPC RegistersÑSupervisor Registers... A-2 MPC8260-Specific SPRs ... A-3 MOTOROLA CONTENTS Title Appendix A Glossary Index Contents Page Number...
  • Page 32 CONTENTS Paragraph Page Title Number Number xxxii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 33 1-10 High-Performance Communication... 1-16 1-11 High-Performance System Microprocessor Configuration ... 1-17 MPC8260 Integrated Processor Core Block Diagram... 2-2 MPC8260 Programming ModelÑRegisters... 2-10 Hardware Implementation Register 0 (HID0) ... 2-11 Hardware Implementation Register 1 (HID1) ... 2-15 Hardware Implementation-Dependent Register 2 (HID2) ... 2-15 Data Cache Organization ...
  • Page 34 Configuring a Single Chip from EPROM ... 5-10 Configuring Multiple Chips... 5-11 MPC8260 External Signals... 6-2 PowerPC Signal Groupings ... 7-2 Single MPC8260 Bus Mode ... 8-3 60x-Compatible Bus Mode... 8-4 Basic Transfer Protocol ... 8-5 Address Bus Arbitration with External Bus Master ... 8-9 Address Pipelining...
  • Page 35 SDRAM Write-after-Write Pipelined, Page Hit ... 10-45 10-36 SDRAM Read-after-Write Pipelined, Page Hit... 10-45 10-37 SDRAM Mode-Set Command Timing... 10-46 10-38 Mode Data Bit Settings... 10-47 10-39 SDRAM Bank-Staggered CBR Refresh Timing ... 10-48 10-40 GPCM-to-SRAM ConÞguration... 10-52 MOTOROLA ILLUSTRATIONS Title Illustrations Page Number xxxv...
  • Page 36 Exception Cycle... 10-89 10-75 FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN) ... 10-91 10-76 MPC8260/EDO Interface Connection to the 60x Bus... 10-92 10-77 Single-Beat Read Access to EDO DRAM... 10-93 10-78 Single-Beat Write Access to EDO DRAM... 10-94...

  • Page 37: Features

    Observe-Only Input Pin Cell (I.Obs)... 12-4 12-5 Output Control Cell (IO.CTL)... 12-5 12-6 General Arrangement of Bidirectional Pin Cells... 12-5 13-1 MPC8260 CPM Block Diagram... 13-3 13-2 Communications Processor (CP) Block Diagram ... 13-5 13-3 RISC Controller Configuration Register (RCCR)... 13-8 13-4 RISC Time-Stamp Control Register (RTSCR)...
  • Page 38 IDMAx ChannelÕs BD Table... 18-15 18-8 DCM Parameters ... 18-18 18-9 IDMA Event/Mask Registers (IDSR/IDMR) ... 18-23 18-10 IDMA BD Structure ... 18-23 19-1 SCC Block Diagram ... 19-2 xxxviii ILLUSTRATIONS Title MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 39 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ... 21-21 21-14 HDLC Bus Transmission Line Configuration ... 21-21 21-15 Delayed RTS Mode ... 21-22 21-16 HDLC Bus TDM Transmission Line Configuration ... 21-22 22-1 Classes of BISYNC Frames... 22-1 MOTOROLA ILLUSTRATIONS Title Illustrations Page Number xxxix...
  • Page 40 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)... 24-21 24-10 Ethernet Interrupt Events Example... 24-22 25-1 LocalTalk Frame Format ... 25-1 25-2 Connecting the MPC8260 to LocalTalk ... 25-3 26-1 SMC Block Diagram ... 26-2 26-2 SMC Mode Registers (SMCMR1/SMCMR2)... 26-3 26-3 SMC Memory Structure ...
  • Page 41 VP Pointer Address Compression ... 29-18 29-8 VC Pointer Address Compression ... 29-18 29-9 ATM Address Recognition Flowchart... 29-19 29-10 MPC8260Õs ABR Basic Model ... 29-20 29-11 ABR Transmit Flow ... 29-22 29-12 ABR Transmit Flow (Continued) ... 29-23 29-13 ABR Transmit Flow (Continued) ...
  • Page 42 UTOPIA Master Mode Signals ... 29-82 29-58 UTOPIA Slave Mode Signals... 29-83 29-59 FCC ATM Mode Register (FPSMR)... 29-86 29-60 ATM Event Register (FCCE)/FCC Mask Register (FCCM) ... 29-88 xlii ILLUSTRATIONS Title MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 43 AAL1 SRTS Clock Recovery Using External Logic ... 29-92 30-1 Ethernet Frame Structure ... 30-1 30-2 Ethernet Block Diagram ... 30-3 30-3 Connecting the MPC8260 to Ethernet... 30-5 30-4 Ethernet Address Recognition Flowchart ... 30-16 30-5 FCC Ethernet Mode Registers (FPSMR) ... 30-20 30-6 Ethernet Event Register (FCCE)/Mask Register (FCCM) ...
  • Page 44 Port Data Direction Register (PDIR) ... 35-3 35-4 Port Pin Assignment Register (PPARAÐPPARD) ... 35-4 35-5 Special Options Registers (PSORAÐPOSRD)... 35-5 35-6 Port Functional Operation... 35-6 35-7 Primary and Secondary Option Programming... 35-8 xliv ILLUSTRATIONS Title MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 45 HID2 Field Descriptions... 2-15 Exception Classifications for the Processor Core... 2-24 Exceptions and Conditions ... 2-24 Integer Divide Latency ... 2-30 Major Differences between MPC8260Õs Core and the MPC603e UserÕs Manual... 2-30 Internal Memory Map... 3-1 Acronyms and Abbreviated Terms ... II-ii System Configuration and Protection Functions ...
  • Page 46 Reset Actions for Each Reset Source ... 5-2 RSR Field Descriptions ... 5-4 RMR Field Descriptions ... 5-5 RSTCONF Connections in Multiple-MPC8260 Systems ... 5-6 Configuration EPROM Addresses... 5-7 Hard Reset Configuration Word Field Descriptions ... 5-8 Acronyms and Abbreviated Terms ...III-iii External Signals ...
  • Page 47 12-2 Boundary Scan Bit Definition ... 12-6 12-3 Instruction Decoding ... 12-29 Acronyms and Abbreviated Terms ... IV-v 13-1 Possible MPC8260 Applications ... 13-3 13-2 Peripheral Prioritization... 13-6 13-3 RISC Controller Configuration Register Field Descriptions... 13-8 13-4 RTSCR Field Descriptions ... 13-10 13-5 RISC Microcode Revision Number...
  • Page 48 IDSR/IDMR Field Descriptions ... 18-23 18-10 IDMA BD Field Descriptions... 18-24 18-11 IDMA Bus Exceptions... 18-27 18-12 Parallel I/O Register ProgrammingÑPort C ... 18-28 18-13 Parallel I/O Register ProgrammingÑPort A ... 18-28 xlviii TABLES Title MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 49 Receive Commands ... 22-5 22-4 Control Character Table and RCCM Field Descriptions... 22-7 22-5 BSYNC Field Descriptions... 22-8 22-6 BDLE Field Descriptions ... 22-9 22-7 Receiver SYNC Pattern Lengths of the DSR ... 22-9 MOTOROLA TABLES Title Tables Page Number xlix...
  • Page 50 SMC Transparent Error Conditions... 26-25 26-13 SMC Transparent RxBD Field Descriptions ... 26-26 26-14 SMC Transparent TxBD... 26-27 26-15 SMC Transparent TxBD Field Descriptions ... 26-27 26-16 SMCE/SMCM Field Descriptions... 26-28 TABLES Title MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 51 Performance Monitoring Cell Fields ... 29-30 29-11 ATM Parameter RAM Map... 29-38 29-12 UEAD_OFFSETs for Extended Addresses in the UDC Extra Header ... 29-40 29-13 VCI Filtering Enable Field Descriptions ... 29-40 29-14 GMODE Field Descriptions ... 29-41 MOTOROLA TABLES Title Tables Page Number...
  • Page 52 30-2 Ethernet-Specific Parameter RAM ... 30-9 30-3 Transmit Commands... 30-12 30-4 Receive Commands ... 30-13 30-5 RMON Statistics and Counters... 30-14 30-6 Transmission Errors... 30-19 30-7 Reception Errors ... 30-19 TABLES Title MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...
  • Page 53 Port B Dedicated Pin Assignment (PPARB = 1)... 35-12 35-7 Port C Dedicated Pin Assignment (PPARC = 1)... 35-14 35-8 Port D Dedicated Pin Assignment (PPARD = 1) ... 35-17 User-Level PowerPC Registers (Non-SPRs)... A-1 User-Level PowerPC SPRs... A-1 MOTOROLA TABLES Title Tables Page Number liii...
  • Page 54 Table Number Supervisor-Level PowerPC Registers (Non-SPR)... A-2 Supervisor-Level PowerPC SPRs... A-2 MPC8260-Specific Supervisor-Level SPRs ... A-3 TABLES Title MPC8260 PowerQUICC II UserÕs Manual Page Number MOTOROLA...

  • Page 55: About This Book

    Audience This manual is intended for software and hardware developers and application programmers who want to develop products for the MPC8260. It is assumed that the reader has a basic understanding of computer networking, OSI layers, and RISC architecture. In addition, it is assumed that the reader has a basic understanding of the communications protocols described here.

  • Page 56: Organization

    60x bus conÞguration. Ñ Chapter 5, ÒReset,Ó describes the behavior of the MPC8260 at reset and start-up. ¥ Part III, ÒThe Hardware Interface,Ó describes external signals, clocking, memory control, and power management of the MPC8260.
  • Page 57 (BRGs) that can be used with the FCCs, SCCs, and SMCs. Ñ Chapter 17, ÒTimers,Ó describes the MPC8260 timer implementation, which can be conÞgured as four identical 16-bit or two 32-bit general-purpose timers. Ñ Chapter 18, ÒSDMA Channels and IDMA Emulation,Ó describes the two physical serial DMA (SDMA) channels on the MPC8260.
  • Page 58 MPC8260Õs fast communications controllers (FCCs), which are SCCs optimized for synchronous high-rate protocols. Ñ Chapter 29, ÒATM Controller,Ó describes the MPC8260 ATM controller, which provides the ATM and AAL layers of the ATM protocol. The ATM controller performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and AAL0, and most of the common parts convergence sublayer (CP-CS) of these protocols.

  • Page 59: Suggested Reading

    This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC8xx Documentation Supporting documentation for the MPC8260 can be accessed through the world-wide web at http://www.mot.com/netcomm. This documentation includes technical speciÞcations, reference materials, and detailed applications notes.

  • Page 60: Conventions

    In certain contexts, such as in a signal encoding or a bit Þeld, indicates a donÕt care. Used to express an undeÞned numerical value  NOT logical operator & AND logical operator OR logical operator MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 61: Acronyms And Abbreviations

    Register used for determining the source of a DSI exception DTLB Data translation lookaside buffer Effective address EEST Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory Floating-point register FPSCR Floating-point status and control register MOTOROLA Meaning About This Book...
  • Page 62 ModiÞed/exclusive/shared/invalidÑcache coherency protocol Memory management unit Most-signiÞcant byte Most-signiÞcant bit Machine state register Not a number Next instruction address NMSI Nonmultiplexed serial interface No-op No operation Operating environment architecture Open systems interconnection lxii Meaning MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 63 SRR0 Machine status save/restore register 0 SRR1 Machine status save/restore register 1 Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UIMM Unsigned immediate value MOTOROLA Meaning About This Book lxiii...

  • Page 64: Powerpc Architecture Terminology Conventions

    Problem mode (or problem state) Real address Relocation Storage (locations) Storage (the act of) lxiv Meaning DSI exception SimpliÞed mnemonics ISI exception Exception Supervisor-level privilege User-level privilege Physical address Translation Memory Access MPC8260 PowerQUICC II UserÕs Manual This Manual MOTOROLA...
  • Page 65 Table iii describes instruction Þeld notation conventions used in this manual. Table iii. Instruction Field Conventions The Architecture SpeciÞcation BA, BB, BT BF, BFA RA, RB, RT, RS /, //, /// MOTOROLA Equivalent to: crbA, crbB, crbD (respectively) crfD, crfS (respectively) rA, rB, rD, rS (respectively) SIMM UIMM 0...0 (shaded)
  • Page 66 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 67: Intended Audience

    Intended Audience Part I is intended for readers who need a high-level understanding of the MPC8260. Contents Part I provides a high-level description of the MPC8260, describing general operation and listing basic features. ¥ Chapter 1, ÒOverview,Ó provides a high-level description of MPC8260 functions and features.
  • Page 68 Data translation lookaside buffer Effective address FCCÔ Fast communications controller Floating-point register GPCM General-purpose chip-select machine General-purpose register HDLC High-level data link control Inter-integrated circuit IEEE Institute of Electrical and Electronics Engineers Part I-lxviii MPC8260 PowerQUICC II UserÕs Manual Meaning MOTOROLA...
  • Page 69 Serial interface System interface unit Serial management controller Serial peripheral interface Special-purpose register SRAM Static random access memory Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner MOTOROLA Meaning Part I. Overview Part I. Overview Part I-lxix...
  • Page 70 Part I. Overview Table iv. Acronyms and Abbreviated Terms (Continued) Term Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine Virtual environment architecture Part I-lxx MPC8260 PowerQUICC II UserÕs Manual Meaning MOTOROLA...

  • Page 71: Features

    MPC860, with the addition of three high-performance communication channels that support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet). MPC8260 has dedicated hardware that can handle up to 256 full-duplex, time-division- multiplexed logical channels This document describes the functional operation of MPC8260, with an emphasis on peripheral functions.
  • Page 72 Ñ Hardware bus monitor and software watchdog timer Ñ IEEE 1149.1 JTAG test access port ¥ Twelve-bank memory controller Ñ Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-deÞnable peripherals MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 73 MPC860, supporting the digital portions of the following protocols: Ð Ethernet/IEEE 802.3 CDMA/CS Ð HDLC/SDLC and HDLC bus Ð Universal asynchronous receiver transmitter (UART) Ð Synchronous UART Ð Binary synchronous (BiSync) communications Ð Transparent MOTOROLA Chapter 1. Overview Part I. Overview...

  • Page 74: Mpc8260Õs Architecture Overview

    Ñ Four independent 16-bit timers that can be interconnected as two 32-bit timers 1.2 MPC8260Õs Architecture Overview The MPC8260 has two external buses to accommodate bandwidth requirements from the high-speed system core and the very fast communications channels. As shown in Figure 1-1, the MPC8260 has three major functional blocks: ¥...

  • Page 75: Mpc603E Core

    This helps ensure coherency between the CPM and system core. The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64- bit split-transaction external data bus, which is connected directly to the external MPC8260 pins.

  • Page 76: System Interface Unit (Siu)

    200 MHz (compared to 86 MIPS of the MPC860 at 66 MHz). The MPC603e core can be disabled. In this mode, the MPC8260 functions as a slave peripheral to an external core or to another MPC8260 device with its core enabled.

  • Page 77: Software Compatibility Issues

    SCCs, three FCCs, and two SMCs. 1.3 Software Compatibility Issues As much as possible, the MPC8260 CPM features were made similar to those of the previous devices (MPC860). The code ßow ports easily from previous devices to the MPC8260, except for new protocols supported by the MPC8260.
  • Page 78 QREQ<¾¾¾ 1 CLKIN¾¾¾> 1 TRIS¾¾¾> 1 BNKSEL[0]/TC[0]/AP[1]/MODCK1<¾¾> 1 BNKSEL[1]/TC[1]/AP[2]/MODCK2<¾¾> 1 BNKSEL[2]/TC[2]/AP[3]/MODCK3<¾¾> 1 TERM[0Ð1] ¾¾¾> 2 Figure 1-2. MPC8260 External Signals MPC8260 PowerQUICC II UserÕs Manual NOTE 32 <¾¾> A[0Ð31] 5 <¾¾> TT[0Ð4] 4 <¾¾> TSIZ[0Ð3] 1 <¾¾> TBST 1 <¾¾> GBL/IRQ1 1 <¾¾>...

  • Page 79: Differences Between Mpc860 And Mpc8260

    1.4 Differences between MPC860 and MPC8260 The following MPC860 features are not included in the MPC8260. ¥ On-chip crystal oscillators (must use external oscillator) ¥ 4-MHz oscillator (input clock must be at the bus speed) ¥ Low power (stand-by) modes ¥...

  • Page 80: Mpc8260 Configurations

    Slow bit-rate protocols do not signiÞcantly affect those numbers. Table 1-2 describes a few options to conÞgure the fast communications channels on the MPC8260. The frequency speciÞed is the minimum CPM frequency necessary to run the mentioned protocols concurrently at full-duplex.

  • Page 81: Mpc8260 Application Examples

    FCCs can also be used to run slower HDLC or 10 BaseT, for example. The CPÕs RISC architecture has the advantage of using common hardware resources for all FCCs. 1.7 MPC8260 Application Examples The MPC8260 can be conÞgured to meet many system application needs, as shown in the following sections. 1.7.1 Examples of Communication Systems Communication examples: ¥...

  • Page 82: Regional Office Router

    Part I. Overview In this application, eight TDM ports are connected to external framers. In the MPC8260, each group of four ports support up to 128 channels. One TDM interface can support 32Ð 128 channels. The MPC8260 receives and transmits data in transparent or HDLC mode, and stores or retrieves the channelized data from memory.

  • Page 83: Lan-To-Wan Bridge Router

    In this application, the MPC8260 is connected to four TDM interfaces channalizing up to 128 channels. Each TDM port supports 32Ð128 channels. If 128 channels are needed, each TDM port can be conÞgured to support 32 channels. This example has two MII ports for 10/100 BaseT LAN connections.

  • Page 84: Cellular Base Station

    Comm Figure 1-6. Cellular Base Station Configuration Here the MPC8260 channelizes two E1s (up to 256, 16-Kbps channels). The local bus can control a bank of DSPs. Data to and from the DSPs can be transferred through the parallel bus to the host port of the DSPs with the internal virtual IDMA.

  • Page 85: Sonet Transmission Controller

    The MPC8260 CPM supports a total aggregate throughput of 710 Mbps at 133 MHz. This includes two full-duplex 100 BaseT and one full-duplex 155 Mbps for ATM. The MPC603e core can operate at a different (higher) speed, if the application requires it.

  • Page 86: High-Performance Communication

    155 Mbps Figure 1-9. Basic System Configuration 1.7.2.2 High-Performance Communication Figure 1-10 shows a high-performance communication conÞguration. 155 Mbps 155 Mbps Figure 1-10. High-Performance Communication 1-16 MPC8260 PowerQUICC II UserÕs Manual MPC8260 SDRAM/SRAM/DRAM/Flash 60x Bus Communication Channels Local Bus UTOPIA...

  • Page 87: High-Performance System Microprocessor

    Serial throughput is enhanced by connecting one MPC8260 in master or slave mode (with system core enabled or disabled) to another MPC8260 in master mode with the core enabled. The core in MPC8260 A can access the memory on the local bus of MPC8260 B. 1.7.2.3 High-Performance System Microprocessor Figure 1-11 shows a conÞguration with a high-performance system microprocessor...
  • Page 88 Part I. Overview 1-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 89: Powerpc Processor Core

    Chapter 2 PowerPC Processor Core The MPC8260 contains an embedded version of the PowerPC 603eª processor. This chapter provides an overview of the basic functionality of the processor core. For detailed information regarding the processor refer to the following: ¥ MPC603e & EC603e UserÕs Manual (Those chapters that describe the...
  • Page 90 Touch Load Buffer Copyback Buffer Figure 2-1. MPC8260 Integrated Processor Core Block Diagram The processor core is a superscalar processor that can issue and retire as many as three instructions per clock. Instructions can execute out of order for increased performance;...

  • Page 91: Powerpc Processor Core Features

    TLB and BAT array, the BAT translation takes priority. As an added feature to the MPC603e core, the MPC8260 can lock the contents of 1Ð3 ways in the instruction and data cache (or an entire cache). For example, this allows embedded applications to lock interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache.
  • Page 92 Ñ A 32- or 64-bit, split-transaction external data bus with burst transfers Ñ Support for one-level address pipelining and out-of-order bus transactions Ñ Hardware support for misaligned little-endian accesses Ñ Added bus multipliers of 4.5x, 5x, 5.5x, 6x, 6.5x 7x, 7.5x, 8x. See Figure 2-3. MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 93: Instruction Unit

    The instruction queue (IQ), shown in Figure 2-1, holds as many as six instructions and loads up to two instructions from the instruction unit during a single cycle. The instruction fetch unit continuously loads as many instructions as space in the IQ allows. Instructions MOTOROLA Chapter 2. PowerPC Processor Core Part I. Overview...

  • Page 94: Branch Processing Unit (Bpu)

    Stalls due to contention for GPRs are minimized by the automatic allocation of rename registers. The processor core writes the contents of the rename registers to the appropriate GPR when integer instructions are retired by the completion unit. MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 95: Load/Store Unit (Lsu)

    An available completion buffer is a required resource for instruction dispatch; if no completion buffers are available, instruction dispatch stalls. A maximum of two instructions per cycle are completed in order from the queue. MOTOROLA Chapter 2. PowerPC Processor Core...

  • Page 96: Memory Subsystem Support

    This section describes the register organization in the processor core as deÞned by the three programming environments of the PowerPC architectureÑthe user instruction set architecture (UISA), the virtual environment architecture (VEA), and the operating MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 97: Powerpc Register Set

    Data is transferred between memory and registers with explicit load and store instructions only. Figure 2-2 shows the complete MPC8260 register set and the programming environment to which each register belongs. This Þgure includes both the PowerPC register set and the MPC8260-speciÞc registers.
  • Page 98 TBR 268 TBR 269 These implementationÐspecific registers may not be supported by other PowerPC processors or processor cores. Although the MPC8260 does not implement an FPU, the LSU can access FPRs if MSR[FP] = 1. Figure 2-2. MPC8260 Programming ModelÑRegisters 2-10 MPC8260 PowerQUICC II UserÕs Manual...

  • Page 99: Mpc8260-Specific Registers

    2.3.1.2 MPC8260-SpeciÞc Registers The set of registers speciÞc to the MPC603e are also shown in Figure 2-2. Most of these are described in the MPC603e UserÕs Manual and are implemented in the MPC8260 as follows: ¥ MMU software table search registers: DMISS, DCMP, HASH1, HASH2, IMISS, ICMP, and RPA.
  • Page 100 QACK, is asserted back to the processor. Once QACK assertion is detected, the processor enters sleep mode after several processor clocks. At this point, the system logic may turn off the PLL by Þrst conÞguring PLL_CFG[0Ð3] to PLL bypass mode, and then disabling SYSCLK. 2-12 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...
  • Page 101 A cache block invalidated by a snoop remains invalid until the cache is unlocked. To prevent locking during a cache access, a sync must precede the setting of DLOCK. MOTOROLA Chapter 2. PowerPC Processor Core Description Part I.

  • Page 102: Hardware Implementation-Dependent Register 1 (Hid1)

    See Chapter 9, ÒPower Management,Ó of the MPC603e UserÕs Manual for more information. See Chapter 3, ÒInstruction and Data Cache Operation,Ó of the MPC603e UserÕs Manual for more information. 2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) The MPC8260 implementation of HID1 is shown in Figure 2-4. 2-14 MPC8260 PowerQUICC II UserÕs Manual...

  • Page 103: Hardware Implementation-Dependent Register 2 (Hid2)

    24Ð26 DWLCK Data cache way lock. Useful for locking blocks of data into the data cache for time-critical applications where deterministic behavior is required. See Section 2.4.2.3, ÒCache Locking.Ó 27Ð31 Ñ Reserved MOTOROLA Chapter 2. PowerPC Processor Core Ñ Function IWLCK Ñ...

  • Page 104: Processor Version Register (Pvr)

    Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations. In addition to the functionality of the MPC603e, the MPC8260 has additional hardware support for misaligned little-endian accesses. Except for string/multiple load and store instructions, little-endian load/store accesses not on a word boundary generate exceptions under the same circumstances as big-endian requests.
  • Page 105 It also provides for word and double-word operand loads and stores between memory and a set of 32 ßoating-point registers (FPRs). Although the MPC8260 does use the FPRs for 64-bit loads and stores, it does not support ßoating-point arithmetic instructions.

  • Page 106: Mpc8260 Implementation-Specific Instruction Set

    Ñ External Control Out Word Indexed (ecowx) Ñ Store Floating-Point as Integer Word Indexed (stÞwx) The MPC8260 does not provide the hardware support for misaligned eciwx and ecowx instructions provided by the MPC603e processor. An alignment exception is taken if these instructions are not word-aligned.

  • Page 107: Mpc8260 Implementation-Specific Cache Implementation

    MEI (modiÞed/exclusive/invalid) protocol. Each block contains eight 32-bit words. Note that the PowerPC architecture deÞnes the term ÔblockÕ as the cacheable unit. For the MPC8260Õs processor core, the block size is equivalent to a cache line. MOTOROLA Chapter 2. PowerPC Processor Core Part I.
  • Page 108 Typically, memory accesses are weakly orderedÑsequences of operations, including load/ store string and multiple instructions, do not necessarily complete in the order they beginÑ 2-20 MPC8260 PowerQUICC II UserÕs Manual State Words 0Ð7 State Words 0Ð7 State Words 0Ð7...

  • Page 109: Instruction Cache

    Locking only a portion of the cache is accomplished by locking ways within the cache. Locking always begins with the Þrst way (way0) and is sequential. That is, it is valid to lock MOTOROLA Chapter 2. PowerPC Processor Core 2-21...

  • Page 110: Exception Model

    Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the program state from being lost due to a system reset or machine check exception or to 2-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 111: Mpc8260 Implementation-Specific Exception Model

    All exceptions report recoverability through MSR[RI]. 2.5.2 MPC8260 Implementation-SpeciÞc Exception Model As speciÞed by the PowerPC architecture, all processor core exceptions can be described as either precise or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some of which are maskable) are caused by events external to the processorÕs...
  • Page 112 6 Set for a store operation and cleared for a load operation. 11 Set if eciwx or ecowx is used and EAR[E] is cleared. 2-24 MPC8260 PowerQUICC II UserÕs Manual Precise/Imprecise Machine check System reset External interrupt...
  • Page 113 00A00Ð00BFF Ñ System call 00C00 A system call exception occurs when a System Call (sc) instruction is executed. MOTOROLA Chapter 2. PowerPC Processor Core Causing Conditions The effective (logical) address cannot be translated. That is, there is a page fault for this portion of the translation, so an ISI exception must be taken to load the PTE (and possibly the page) into memory.

  • Page 114: Exception Priorities

    3. eciwx or ecowx operand misaligned 4. A multiple or string access is attempted with MSR[LE] set 2.6 Memory Management The following subsections describe the memory management features of the PowerPC architecture and the MPC8260 implementation. 2-26 MPC8260 PowerQUICC II UserÕs Manual Causing Conditions...

  • Page 115: Powerpc Mmu Model

    TLB with memory. In the MPC8260, the processor coreÕs TLBs are 64-entry, two-way set-associative caches that contain instruction and data address translations. The MPC8260Õs core provides hardware assist for software table search operations through the hashed page table on TLB misses.

  • Page 116: Mpc8260 Implementation-Specific Mmu Features

    The MPC8260Õs TLBs are 64-entry, two-way set-associative caches that contain instruction and data address translations. The processor core provides hardware assist for software table search operations through the hashed page table on TLB misses. Supervisor software can invalidate TLB entries selectively.

  • Page 117: Instruction Timing

    Performance of integer divide operations has been improved in the processor core. A divide instruction takes half the cycles to execute as described in the MPC603e UserÕs Manual. MOTOROLA Chapter 2. PowerPC Processor Core Part I. Overview...

  • Page 118: Differences Between The Mpc8260Õs Core And The Powerpc 603E Microprocessor

    2.8 Differences between the MPC8260Õs Core and the PowerPC 603e Microprocessor The MPC8260Õs processor core is a derivative of the MPC603e microprocessor design. Some changes have been made and are visible either to a programmer or a system designer. Any software designed around an MPC603e is functional when replaced with the MPC8260 except for the speciÞc customer-visible changes listed in Table 2-7.
  • Page 119 Table 2-7. Major Differences between MPC8260Õs Core and the MPC603e UserÕs Description Addition of speed-for-power functionality Improved access to cache during block Þlls Improved integer divide latency MOTOROLA Chapter 2. PowerPC Processor Core Manual Impact The processor core implements an additional dynamic power management mechanism.
  • Page 120 Part I. Overview 2-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 121: Memory Map

    The MPC8260's internal memory resources are mapped within a contiguous block of memory. The size of the internal space in the MPC8260 is 128 Kbytes. The location of this block within the global 4-Gbyte real memory space can be mapped on 128 Kbytes resolution through an implementation speciÞc special register called the internal memory...
  • Page 122 Base register bank 4 10124 Option register bank 4 10128 Base register bank 5 1012C Option register bank 5 10130 Base register bank 6 MPC8260 PowerQUICC II UserÕs Manual Name Size 32 bits 8 bits 32 bits 32 bits 32 bits 32 bits...
  • Page 123 Local bus-assigned UPM refresh timer 8 bits 101A4 LSRT Local bus-assigned SDRAM refresh timer 101A8 IMMR Internal memory map register 101ACÐ101FF Reserved Ñ MOTOROLA Name Size 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits...
  • Page 124 System clock control register 10C88 SCMR System clock mode register 10C90 Reset status register 10C94 Reset mode register 10C98Ð10CFF Reserved Ñ MPC8260 PowerQUICC II UserÕs Manual Name Size System Integration Timers 32 bytes 16 bits 32 bits 32 bits 32 bits 16 bytes...
  • Page 125 Reserved Ñ 10D84 TGCR2 Timer 3 and timer 4 global conÞguration register 10D85Ð10D8F Reserved Ñ 10D90 TMR1 Timer 1 mode register MOTOROLA Name Size Input/Output Port 32 bits 32 bits 32 bits 32 bits 32 bits 12 bytes 32 bits...
  • Page 126 11021 Reserved Ñ 11024 IDMR1 IDMA 1 mask register 11025 Reserved Ñ 11028 IDSR2 IDMA 2 event register MPC8260 PowerQUICC II UserÕs Manual Name Size 16 bits 17.2.3/17-6 16 bits 17.2.4/17-7 16 bits 17.2.4/17-7 16 bits 17.2.5/17-8 16 bits 17.2.5/17-8 16 bits 17.2.6/17-8...
  • Page 127 1131D FTIRR1_PHY1 1131E FTIRR1_PHY2 1131F FTIRR1_PHY3 11320 GFMR2 FCC2 general mode register 11324 FPSMR2 FCC2 protocol-speciÞc mode register MOTOROLA Name Size 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits...
  • Page 128 115F4 BRGC6 BRG6 conÞguration register 115F8 BRGC7 BRG7 conÞguration register 115FC BRGC8 BRG8 conÞguration register 11600Ð1185F Reserved Reserved MPC8260 PowerQUICC II UserÕs Manual Name Size 16 bits 28.5/28-7 2 bytes Ñ 16 bits 28.4/28-7 2 bytes Ñ 32 bits 29.13.3/29-87 (ATM) 30.18.2/30-21 (Ethernet)
  • Page 129 BRGC3 BRG3 conÞguration register 119FC BRGC4 BRG4 conÞguration register 11A00 GSMR_L1 SCC1 general mode register 11A04 GSMR_H1 SCC1 general mode register MOTOROLA Name Size 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits 8 bits 24 bits...
  • Page 130 SCCE2 SCC2 event register 11A34 SCCM2 SCC2 mask register 11A37 SCCS2 SCC2 status register 11A38Ð11A3F Reserved Ñ 3-10 MPC8260 PowerQUICC II UserÕs Manual Name Size 16 bits 19.1.2/19-9 20.16/20-13 (UART) 21.8/21-7 (HDLC) 22.11/22-10 (BISYNC) 23.9/23-9 (Transparent) 24.17/24-15 (Ethernet) 2 bytes Ñ...
  • Page 131 TODR4 SCC4 transmit on-demand register 11A6E DSR4 SCC4 data synchronization register 11A70 SCCE4 SCC4 event register 11A74 SCCM4 SCC4 mask register MOTOROLA Name Size SCC3 32 bits 32 bits 16 bits 2 bytes 16 bits 16 bits 16 bits 16 bits...
  • Page 132 11B08 CMXSCR CPM mux SCC clock route register 11B0C CMXSMR CPM mux SMC clock route register 11B0D Reserved Ñ 3-12 MPC8260 PowerQUICC II UserÕs Manual Name Size 8 bits 20.20/20-21 (UART) 21.12/21-14 (HDLC) 22.15/22-16 (BISYNC) 23.13/23-13 (Transparent) 8 bytes Ñ...
  • Page 133 11B4B Reserved Ñ 11B4C SI2STR SI2 status register 11B4D Reserved Ñ 11B4E SI2RSR SI2 RAM shadow address register MOTOROLA Name Size 16 bits 16 bytes SI1 Registers 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits 8 bits...
  • Page 134 Ñ 12C00Ð12DFF SI2RxRAM SI 2 receive routing RAM 12E00Ð12FFF Reserved Ñ 13000Ð137FF Reserved Reserved 13800Ð13FFF Reserved Reserved 3-14 MPC8260 PowerQUICC II UserÕs Manual Name Size MCC2 Registers 16 bits 27.10.1/27-18 16 bits 8 bits 27.8/27-15 1,159 Ñ bytes SI1 RAM 14.4.3/14-10...
  • Page 135 60x bus conÞguration. ¥ Chapter 5, ÒReset,Ó describes the behavior of the MPC8260 at reset and start-up. Suggested Reading Supporting documentation for the MPC8260 can be accessed through the world-wide web at http://www.motorola.com/netcomm and at http://www.mot.com/PowerPC.
  • Page 136 BIST Built-in self test Direct memory access DRAM Dynamic random access memory Effective address General-purpose register IEEE Institute of Electrical and Electronics Engineers Least-signiÞcant byte Least-signiÞcant bit Load/store unit Most-signiÞcant byte Part II-ii MPC8260 PowerQUICC II UserÕs Manual Meaning MOTOROLA...
  • Page 137 Table v. Acronyms and Abbreviated Terms (Continued) Term Most-signiÞcant bit Machine state register Peripheral component interconnect RTOS Real-time operating system Receive Special-purpose register Software watchdog timer Transmit MOTOROLA Meaning Part II. Configuration and Reset Part II. Configuration and Reset Part II-iii...
  • Page 138 Part II. Configuration and Reset Part II-iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 139: System Interface Unit (Siu)

    ¥ Level-two cache controller interface ¥ IEEE 1149.1 test-access port (TAP) Figure 4-1 is a block diagram of the SIU. Core Configuration Registers Communications Processor MOTOROLA 60x Bus (32-Bit Address/64-Bit Data) Counters Bridge Interrupt Controller Local Bus (18-Bit Address/32-Bit Data) Figure 4-1.SIU Block Diagram...

  • Page 140: System Configuration And Protection

    The clock synthesizer generates the clock signals used by the SIU and other MPC8260 modules. The SIU clocking scheme supports stop and normal modes. The 60x bus interface is a standard pipelined bus. The MPC8260 allows external bus masters to request and obtain system bus mastership. Chapter 8, ÒThe 60x Bus,Ó describes bus operation, but 60x bus conÞguration is explained in this section.

  • Page 141: Bus Monitor

    Section 4.3.2, ÒSystem ConÞguration and Protection Registers.Ó 4.1.1 Bus Monitor The MPC8260 has two bus monitors, one for the 60x bus and one for the local bus. The bus monitor ensures that each bus cycle is terminated within a reasonable period. The bus monitor does not count when the bus is idle.

  • Page 142: Timers Clock

    The time counter control and status register (TMCNTSC) is used to enable or disable the various timer functions and report the interrupt source. Figure 4-4 shows a block diagram of TMCNT. MPC8260 PowerQUICC II UserÕs Manual Divide by 4 Divide by 512...

  • Page 143: Periodic Interrupt Timer (Pit)

    If PTE = 0, the PIT cannot count and retains the old count value. The PIT is not affected by reads. Figure 4-5 is a block diagram of the PIT. PISCR[PTE] timersclk Clock for PIT Disable MOTOROLA Chapter 4. System Interface Unit (SIU) Divide by 8,192 PITC 16-Bit Modulus PISCR[PS]...

  • Page 144: Software Watchdog Timer

    Figure 4-6 shows a state diagram for the watchdog timer. Reset Not 0x556C/DonÕt reload Figure 4-6. Software Watchdog Timer Service State Diagram MPC8260 PowerQUICC II UserÕs Manual PITC 1 PITC 1 ------------------------------------- -------------------------...

  • Page 145: Interrupt Controller

    ¥ Three SIU interrupt sources (PIT and TMCNT) ¥ 24 external sources (16 port C and 8 IRQ) ¥ Programmable priority between PIT and TMCNT ¥ Programmable priority between SCCs, FCCs, and MCCs MOTOROLA Chapter 4. System Interface Unit (SIU) SWSR Service...

  • Page 146: Interrupt Configuration

    ¥ Unique vector number for each interrupt source 4.2.1 Interrupt ConÞguration Figure 4-8 shows the MPC8260 interrupt structure. The interrupt controller receives interrupts from internal sources, such as the PIT or TMCNT, from the CPM, and from external pins (port C parallel I/O pins).

  • Page 147: Interrupt Source Priorities

    CPM sub-block event are also maskable. All interrupt sources are prioritized and bits are set in the interrupt pending register (SIPNR). On the MPC8260, the prioritization of the interrupt sources is ßexible in the following two aspects: ¥ The relative priority of the FCCs, SCCs, and MCCs can be modiÞed ¥...
  • Page 148 Part II. ConÞguration and Reset Table 4-2. Interrupt Source Priority Levels (Continued) Priority Level 4-10 MPC8260 PowerQUICC II UserÕs Manual Interrupt Source Description XSIU4 (GSIU = 0) XCC1 XCC2 XCC3 XCC4 XSIU2 (GSIU = 1) XCC5 XCC6 XCC7 XCC8 XSIU5 (GSIU = 0)
  • Page 149 Table 4-2. Interrupt Source Priority Levels (Continued) Priority Level MOTOROLA Chapter 4. System Interface Unit (SIU) Interrupt Source Description SDMA Bus Error IDMA1 YCC2 (Spread) Parallel I/OÐPC12 Parallel I/OÐPC11 IDMA2 Timer 2 Parallel I/OÐPC10 XSIU5 (GSIU = 1) YCC3 (Spread)

  • Page 150: Scc, Fcc, And Mcc Relative Priority

    4.2.2.2 PIT, TMCNT, and IRQ Relative Priority The MPC8260 has seven general-purpose interrupt requests (IRQs), Þve of which, with the PIT, and TMCNT, can be mapped to any XSIU location. IRQ6 and IRQ7 have Þxed priority.

  • Page 151: Highest Priority Interrupt

    Table 4-2 shows which interrupt sources have multiple interrupting events. Figure 4-9 shows an example of how the masking occurs, using an SCC as an example. MOTOROLA Chapter 4. System Interface Unit (SIU) 4-13...

  • Page 152: Interrupt Vector Generation And Calculation

    Table 4-3 lists encodings for the six low-order bits of the interrupt vector. Table 4-3. Encoding the Interrupt Vector Interrupt Number 4-14 MPC8260 PowerQUICC II UserÕs Manual SIPNR 13 Input (or 13 Event Bits) SIMR...
  • Page 153 Table 4-3. Encoding the Interrupt Vector (Continued) Interrupt Number MOTOROLA Chapter 4. System Interface Unit (SIU) Interrupt Source Description IDMA1 IDMA2 IDMA3 IDMA4 SDMA Reserved Timer1 Timer2 Timer3 Timer4 TMCNT Reserved IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Reserved 0b01_1010Ð01_1111...

  • Page 154: Port C External Interrupts

    Requests can be masked independently in the interrupt mask register (SIMR). Notice that the global SIMR is cleared on system reset so pins left ßoating do not cause false interrupts. 4-16 MPC8260 PowerQUICC II UserÕs Manual Interrupt Source Description SCC4...

  • Page 155: Programming Model

    Table 4-2. Bits Field Ñ Reset Addr Figure 4-10. SIU Interrupt Configuration Register (SICR) MOTOROLA Chapter 4. System Interface Unit (SIU) 0000_0000_0000_0000 0x10C00 Part II. ConÞguration and Reset Ñ GSIU SPS 4-17...

  • Page 156: Siu Interrupt Priority Register (Siprr)

    IRQ1ÐIRQ6, PIT, and TMCNT. Bits Field XS1P XS2P Reset Addr Bits Field XS5P XS6P Reset Addr Figure 4-11. SIU Interrupt Priority Register (SIPRR) 4-18 MPC8260 PowerQUICC II UserÕs Manual Description XS3P 0x10C10 XS7P 0x10C12 XS4P Ñ 0000 XS8P Ñ 0000 MOTOROLA...

  • Page 157: Cpm Interrupt Priority Registers (Scprr_H And Scprr_L)

    Field XC1P XC2P Reset Addr Bits Field XC5P XC6P Reset Addr Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H) MOTOROLA Chapter 4. System Interface Unit (SIU) Description XC3P 0x10C14 XC7P 0x10C16 Part II. ConÞguration and Reset XC4P Ñ Ñ XC8P Ñ...
  • Page 158 001 SCC2 asserts its request in the YCC1 position. 010 SCC3 asserts its request in the YCC1 position. 011 SCC4 asserts its request in the YCC1 position. 1XX YCC1 position is not active. 4-20 MPC8260 PowerQUICC II UserÕs Manual Description YC2P YC3P 0x10C18...

  • Page 159: Siu Interrupt Pending Registers (Sipnr_H And Sipnr_L)

    Field RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA Reset Addr These Þelds are zero after reset because their corresponding mask register bits are cleared (disabled). MOTOROLA Description PC7 PC8 PC9 PC10 PC11 PC12 0x10C08 0x10C10 Figure 4-14. SIPNR_H Fields Ñ...

  • Page 160: Siu Interrupt Mask Registers (Simr_H And Simr_L)

    Field Ñ IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Reset Addr Figure 4-17 shows SIMR_L. 4-22 PC9 PC10 PC11 PC12 0000_0000_0000_0000 0x10C1C 0000_0000_0000_0000 0x10C1E Figure 4-16. SIMR_H Register MPC8260 PowerQUICC II UserÕs Manual PC13 PC14 PC15 Ñ TMCNT MOTOROLA Ñ...

  • Page 161: Siu Interrupt Vector Register (Sivec)

    Reset Addr Figure 4-18. SIU Interrupt Vector Register (SIVEC) 4-23 Ñ SCC1 SCC2 SCC3 SCC4 0000_0000_0000_0000 0x10C20 0000_0000_0000_0000 0x10C22 Figure 4-17. SIMR_L Register 0000_0000_0000_0000 0x10C04 0000_0000_0000_0000 0x10C06 MPC8260 PowerQUICC II UserÕs Manual Ñ Ñ TIMER1 TIMER2 TIMER3 TIMER4 Ñ MOTOROLA...

  • Page 162: Siu External Interrupt Control Register (Siexr)

    BASE + n Figure 4-19. Interrupt Table Handling Example Note that the MPC8260 differs from previous MPC8xx implementations in that when an interrupt request occurs, SIVEC can be read. If there are multiple interrupt sources, SIVEC latches the highest priority interrupt. Note that the value of SIVEC cannot change while it is being read.

  • Page 163: System Configuration And Protection Registers

    The bus conÞguration register (BCR), shown in Figure 4-21, contains conÞguration bits for various features and wait states on the 60x bus. 4-25 0000_0000_0000_0000 0x10C24 EDI4 EDI5 EDI6 EDI7 0000_0000_0000_0000 0x10C26 Table 4-8. SIEXR Field Descriptions Description MPC8260 PowerQUICC II UserÕs Manual Ñ MOTOROLA...

  • Page 164: Bus Configuration Register (Bcr)

    60x-bus devices. APD indicates how many cycles the MPC8260 should wait for ARTRY, but because it is assumed that ARTRY can be asserted (by other masters) only on cachable address spaces, APD is considered only on transactions that hit one of the 60x-assigned memory controller banks and have the GBL signal asserted during address phase.
  • Page 165 (compared to internal master, like MPC8260Õs DMA, which drives the address on an internal bus in the chip). Thus, it is assumed that an additional cycle is needed for the memory controllers banks to complete the address match.

  • Page 166: Bus Arbiter Configuration Register (Ppc_Acr)

    4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) The 60x bus arbitration-level registers, shown in Figure 4-23 and Figure 4-24, deÞne arbitration priority of MPC8260 bus masters. Priority Þeld 0 has highest-priority. For information about MPC8260 bus master indexes, see the description of PPC_ACR[PRKM] in Table 4-10.
  • Page 167 0100 Addr PPC_ALRL, shown in Figure 4-24, deÞnes arbitration priority of 60x bus masters 8Ð15. Priority Þeld 0 is the highest-priority arbitration level. For information about the MPC8260 bus master indexes, see the description of PPC_ACR[PRKM] in Table 4-10. Field...

  • Page 168: Local Bus Arbitration Level Registers (Lcl_Alrh And Lcl_Acrl)

    LCL_ACRL) The local bus arbitration level registers (LCL_ALRH and LCL_ALRL), shown in Figure 4-26 and Figure 4-27, deÞnes arbitration priority for MPC8260 local bus masters 0Ð 7. Priority Þeld 0 has highest-priority. For information about the MPC8260 local bus master indexes see LCL_ACR[PRKM] in Table 4-11.
  • Page 169 LPBSE Reset Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó Addr Figure 4-28. SIU Model Configuration Register (SIUMCR) 4-31 MPC8260 PowerQUICC II UserÕs Manual Priority Field 9 Priority Field 10 1001 1010 0x1003C Priority Field 13...
  • Page 170 Parity byte select enable. 0 Parity byte select is disabled. GPL4 output of UPM is available for memory control. 1 Parity byte select is enabled. GPL4 pin is used as parity byte select output from the MPC8260. CDIS Core disable.
  • Page 171 00 No masking on bus request lines. 01 Reserved 10 The MPC8260Õs internal core bus request masked and external bus requests two and three masked (boot master connected to external bus request 1). 11 All external bus requests masked (boot master is the MPC8260Õs internal core).

  • Page 172: Internal Memory Map Register (Immr)

    It would not change if the part is changed to Þx a bug in an existing module. The MPC8260 has an ID of 0x00.

  • Page 173: System Protection Control Register (Sypcr)

    Software watchdog prescale. Controls the divide-by-2,048 software watchdog timer prescaler. 0 The software watchdog timer is not prescaled. 1 The software watchdog timer clock is prescaled. 4-35 SWTC 1111_1111_1111_1111 0x10004 PBME LBME 0x10006 Description MPC8260 PowerQUICC II UserÕs Manual Ñ SWE SWRI SWP 00_0 MOTOROLA...

  • Page 174: Software Service Register (Swsr)

    60x bus monitor time-out. Set when TEA is asserted due to the 60x bus monitor time-out. ISBE Internal space bus error. Indicates that TEA was asserted due to error on a transaction to MPC8260Õs internal memory space. TESCR2[REGS, DPR] indicate which of MPC8260Õs internal slaves caused the error.

  • Page 175: X Bus Transfer Error Status And Control Register 2 (Tescr2)

    The 60x bus transfer error status and control register 2 (TESCR2) is shown in Figure 4-32. Bits Field Ñ REGS Reset Addr Bits Field Reset Addr Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2) 4-37 MPC8260 PowerQUICC II UserÕs Manual Description Ñ 0000_0000_0000_0000 0x10044 0000_0000_0000_0000 0x10046 Ñ MOTOROLA...

  • Page 176: Local Bus Transfer Error Status And Control Register 1 (L_Tescr1)

    3Ð6 Ñ Reserved, should be cleared. Local bus bridge error. An error occurred in a transaction to the MPC8260Õs 60x bus to local bus bridge. 8Ð15 Parity error on byte. There are eight parity error status bits, one per 8-bit lane. A bit is set for the byte that had a parity error.

  • Page 177: Local Bus Transfer Error Status And Control Register 2 (L_Tescr2)

    The local bus transfer error status and control register 2 (L_TESCR2) is shown in Figure 4-34. Bits Field Reset Addr Bits Field Reset Addr Figure 4-34. Local Bus Transfer Error Status and Control Register 2 (L_TESCR2) 4-39 MPC8260 PowerQUICC II UserÕs Manual Description Ñ 0000_0000_0000_0000 0x1004C 0000_0000_0000_0000 0x1004E Ñ MOTOROLA...

  • Page 178: Time Counter Status And Control Register (Tmcntsc)

    0 The time counter does not generate an interrupt when SEC is set. 1 The time counter generates an interrupt when SEC is set. Alarm interrupt enable. If ALE = 1, the time counter generates an interrupt when ALR is set. 4-40 MPC8260 PowerQUICC II UserÕs Manual Description SEC ALR 0000_0000_0000_0000...

  • Page 179: Time Counter Register (Tmcnt)

    4.3.2.16 Time Counter Alarm Register (TMCNTAL) The time counter alarm register (TMCNTAL), shown in Figure 4-37, holds a value (ALARM). When the value of TMCNT equals ALARM, a maskable interrupt is generated. 4-41 MPC8260 PowerQUICC II UserÕs Manual Description TMCNT Ñ...

  • Page 180: Periodic Interrupt Registers

    It also contains the controls for the 16 bits to be loaded in a modulus counter. Bits Field Ñ Reset Addr Figure 4-38. Periodic Interrupt Status and Control Register (PISCR) 4-42 MPC8260 PowerQUICC II UserÕs Manual ALARM Ñ 0x1022C ALARM Ñ 0x1222E Description 0000_0000_0000_0000 0x10240 Ñ...

  • Page 181: Periodic Interrupt Timer Count Register (Pitc)

    The periodic interrupt timer count register (PITC), shown in Figure 4-39, contains the 16 bits to be loaded in a modulus counter. Bits Field Reset Addr Bits Field Reset Addr Figure 4-39. Periodic interrupt Timer Count Register (PITC) 4-43 MPC8260 PowerQUICC II UserÕs Manual Description PITC 0000_0000_0000_0000 0x10244 Ñ 0000_0000_0000_0000 0x10246 MOTOROLA...

  • Page 182: Periodic Interrupt Timer Register (Pitr)

    Ñ Reserved, should be cleared. 4.4 SIU Pin Multiplexing Some functions share pins. The actual pinout of the MPC8260 is shown in the hardware speciÞcations. The control of the actual functionality used on a speciÞc pin is shown in 4-44 MPC8260 PowerQUICC II UserÕs Manual...
  • Page 183 LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LSDRAS/LOE LGPL3/LSDCAS LPBS/LGPL4/LUPWAIT/LGTA LGPL5/LSDAMUX MOTOROLA Chapter 4. System Interface Unit (SIU) Part II. ConÞguration and Reset Pin ConÞguration Control Controlled by SIUMCR programming see Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR),Ó for more details. Controlled dynamically according to the speciÞc memory controller machine that handles the current bus transaction.
  • Page 184 Part II. ConÞguration and Reset 4-46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 185: Reset Causes

    Hard reset This is a bidirectional I/O pin. The MPC8260 can detect an external assertion of HRESET only if it (HRESET) occurs while the MPC8260 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-collector pin.

  • Page 186: Reset Actions

    The MPC8260 asserts HRESET and SRESET throughout the power-on reset process, including conÞguration. ConÞguration takes 1,024 CLOCKIN cycles, after which MODCK[1Ð3] are sampled to determine the chips working mode. Next the MPC8260 halts until the main PLL locks. As described in Section 9.2, ÒClock ConÞguration,Ó the main PLL locks according to MODCK[1Ð3], which are sampled, and to MODCK_HI...

  • Page 187: Hreset Flow

    SRESET; after negation is detected, a 16-cycle period is taken before testing the presence of an external (hard/soft) reset. While SRESET is asserted, internal hardware is reset but hard reset conÞguration does not change. MOTOROLA MODCK[1Ð3] are sampled. MODCK_HI...

  • Page 188: Reset Status Register (Rsr)

    BMRS is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it (writing zero has no effect). 0 No bus monitor reset event has occurred 1 A bus monitor reset event has occurred MPC8260 PowerQUICC II UserÕs Manual Ñ 0000_0000_0000_0000 0x10C90...

  • Page 189: Reset Mode Register (Rmr)

    Setting CSRE conÞgures the chip to perform a hard reset sequence whenever the core enters checkstop state. 0 Reset not generated when core enters checkstop state. 1 Reset generated when core enters checkstop state. MOTOROLA Function Ñ 0000_0000_0000_0000 0x10C94 Ñ...
  • Page 190 The 32-bit hard reset conÞguration word is described in Section 5.4.1, ÒHard Reset ConÞguration Word.Ó The reset conÞguration sequence is designed to support a system that uses up to eight MPC8260 chips, each conÞgured differently. It needs no additional glue logic for reset conÞguration.
  • Page 191 Table 5-6 shows addresses that should be used to conÞgure the various MPC8260s. Byte addresses that do not appear in this table have no effect on the conÞguration of the MPC8260 chips. The values of the bytes in Table 5-6 are always read on byte lane D[0Ð7] regardless of the port size.

  • Page 192: Reset Configuration

    1 MSR[IP] = 0 Exceptions are vectored to the physical address 0x000n_nnnn. ISPS Internal space port size. DeÞnes the initial value of BCR[ISPS]. Setting ISPS conÞgures the MPC8260 to respond to accesses from a 32-bit external master to its internal space. See Section 4.3.2.1, ÒBus ConÞguration Register (BCR).Ó 8Ð9 L2CPC L2 cache pins conÞguration.

  • Page 193: Hard Reset Configuration Examples

    This is the simplest conÞguration scenario. It can be used if the default values achieved by clearing the hard reset conÞguration word are desired. This is applicable only for systems using single-MPC8260 bus mode (as opposed to 60x bus mode). To enter this mode, tie RSTCONF to V as shown in Figure 5-4.

  • Page 194: Single Mpc8260 Configured From Boot Eprom

    Figure 5-4. Single Chip with Default Configuration 5.4.2.2 Single MPC8260 ConÞgured from Boot EPROM For a conÞguration that differs from the default, the MPC8260 can be used as a conÞguration master by tying RSTCONF to GND as shown in Figure 5-5. The MPC8260 can access the boot EPROM.
  • Page 195 Configuration Slave Chip 1 HRESET PORESET Configuration Slave Chip 2 HRESET PORESET Configuration Slave Chip 7 HRESET PORESET Figure 5-6. Configuring Multiple Chips MOTOROLA Part II. ConÞguration and Reset EPROM Control Signals A[0Ð31] D[0Ð31] RSTCONF D[0Ð31] RSTCONF D[0Ð31] RSTCONF D[0Ð31] RSTCONF Chapter 5.

  • Page 196: Multiple Mpc8260S In A System With No Eprom

    5.4.2.4 Multiple MPC8260s in a System with No EPROM In some cases, the conÞguration master capabilities of the MPC8260 cannot be used. This can happen for example if there is no boot EPROM in the system or the boot EPROM is not controlled by an MPC8260.
  • Page 197 Intended Audience Part III is intended for system designers who need to understand how each MPC8260 signal works and how those signals interact. Contents Part III describes external signals, clocking, memory control, and power management of the MPC8260. It contains the following chapters: ¥...
  • Page 198 This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC8xx Documentation Supporting documentation for the MPC8260 can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical speciÞcations, reference materials, and detailed applications notes.
  • Page 199 IEEE Institute of Electrical and Electronics Engineers IrDA Infrared Data Association ISDN Integrated services digital network JTAG Joint Test Action Group LIFO Last-in-Þrst-out Least recently used MOTOROLA Meaning Part III. The Hardware Interface Part III. The Hardware Interface Part III-iii...
  • Page 200 System interface unit Serial management controller Systems network architecture. Serial peripheral interface Special-purpose register SRAM Static random access memory Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter Part III-iv MPC8260 PowerQUICC II UserÕs Manual Meaning MOTOROLA...
  • Page 201 Table vi. Acronyms and Abbreviated Terms (Continued) Term UISA User instruction set architecture User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter MOTOROLA Meaning Part III. The Hardware Interface Part III. The Hardware Interface Part III-v...
  • Page 202 Part III. The Hardware Interface Part III-vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 203: External Signals

    Chapter 8, ÒThe 60x Bus.Ó 6.1 Functional Pinout Figure 6-1 shows MPC8260 signals grouped by function. Note that many of these signals are multiplexed and this Þgure does not indicate how these signals are multiplexed.

  • Page 204: Signal Descriptions

    Figure 6-1. MPC8260 External Signals 6.2 Signal Descriptions The MPC8260 system bus, shown in Table 6-1, consists of all the signals that interface with the external bus. Many of these pins perform different functions, depending on how the user assigns them.
  • Page 205 Following an AACK, which terminates the address bus tenure, the MPC8260 negates ABB for a fraction of a bus cycle and than stops driving this pin. As an input the MPC8260 will not assume 60x bus ownership as long as it senses this pin is asserted by an external 60x bus master.
  • Page 206 Following a TA, which terminates the data bus tenure, the MPC8260 negates DBB for a fraction of a bus cycle and than stops driving this pin. As an input, the MPC8260 does not assume 60x data bus ownership as long as it senses DBB asserted by an external 60x bus master.
  • Page 207 5 and D[40Ð47]. Time base enableÑThis is a count enable input to the Time Base counter in the core. External data bus grant 3Ñ(Output) The MPC8260 asserts this pin to grant 60x data bus ownership to an external bus master.
  • Page 208 MPC2605GA L2 cache if the internal arbiter is used (BCR[EARB] = 0). If an external arbiter is used in this MPC8260, the CPU_DBG input of the L2 cache should be connected to the DBG driven from the external arbiter to this MPC8260.
  • Page 209 60x bus SDRAM address multiplexerÑThis output pin controls the 60x SDRAM address multiplexer PGPL5 when the MPC8260 is in external master mode. 60x bus UPM general purpose line 5ÑThis is one of six general purpose output lines from UPM. The values and timing of this pin is programmed in the UPM.
  • Page 210 PCI parityÑPCI parity input/output pin. Assertion of this pin indicates that odd parity is driven across PCI_AD[0Ð31] and PCI_C/BE[0Ð3] during address and data phases. Negation of PCI_PAR indicates that even parity is driven across the PCI_AD[0Ð31] and PCI_C/BE[0Ð3] during address and data phases. MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...
  • Page 211 PCI frameÑPCI cycle frame input output pin. Used by the current PCI master to indicate the beginning and duration of an access. Driven by the MPC8260 when its PCI interface is the master of the access. Otherwise, it is an input.
  • Page 212 PCI INTAÑ(Input/output) When the MPC8260 is the host in the PCI system, this pin is an input for delivering PCI interrupts to the host. When the MPC8260 is not the host of the PCI system, this pin is an output used by the MPC8260 to signal an interrupt to the PCI host.
  • Page 213 Hard resetÑThis open drain line, when asserted causes the MPC8260 to enter hard reset state. SRESET Soft resetÑThis open drain line, when asserted causes the MPC8260 to enter the soft reset state. QREQ Quiescent requestÑ Output only. Indicates that MPC8260Õs internal core is about to enter its low power mode.
  • Page 214 Transfer code 1ÑThe transfer code output pins supply information that can be useful for debug purposes for each of the MPC8260Õs initiated bus transactions. Bank select 1ÑThe bank select outputs are used for selecting SDRAM bank when the MPC8260 is in 60x-compatible bus mode.
  • Page 215 The 60x bus signals used with MPC8260 are grouped as follows: ¥ Address arbitration signalsÑIn external arbiter mode, MPC8260 uses these signals to arbitrate for address bus mastership. The MPC8260 arbiter uses these signals to enable an external device to arbitrate for address bus mastership.
  • Page 216 Þnal data beat. 7.1 Signal ConÞguration Figure shows the grouping of the MPC8260Õs 60x bus signal conÞguration. The MPC8260 hardware speciÞcations provides a pinout showing pin numbers. These are shown in Figure 7-1.

  • Page 217: Signal Descriptions

    Bus arbitration signals have no meaning in internal-only mode. 7.2.1.1 Bus Request (BR)ÑOutput The bus request (BR) signal is both an input and an output signal on the MPC8260. 7.2.1.1.1 Address Bus Request (BR)ÑOutput Following are the state meaning and timing comments for the BR signal output in external master mode.

  • Page 218: Address Bus Request (Br)Ñinput

    BR is not required for a qualiÞed bus grant (for bus parking). NegatedÑIndicates that the MPC8260 is not granted next address ownership. Timing Comments AssertionÑMay occur on any cycle. Once the MPC8260 has assumed address bus ownership, it does not begin checking for BG again until the cycle after AACK.

  • Page 219: Bus Grant (Bg)Ñoutput

    NegationÑMay occur whenever the MPC8260 must be prevented from using the address bus. The MPC8260 may still assume address bus ownership on the cycle BG is negated if it was asserted the previous cycle with other bus grant qualiÞcations. 7.2.1.2.2 Bus Grant (BG)ÑOutput Following are the state meaning and timing comments for the BG signal output in external master mode.

  • Page 220: Address Bus Busy (Abb)Ñinput

    Address transfer start signal are input and output signals that indicate that an address bus transfer has begun. 7.2.2.1 Transfer Start (TS) The TS signal is both an input and an output signal on the MPC8260. 7.2.2.1.1 Transfer Start (TS)ÑOutput Following are the state meaning and timing comments for the TS output signal.

  • Page 221: Address Transfer Signals

    For a detailed description of how these signals interact, see Section 7.2.4, ÒAddress Transfer Attribute Signals.Ó MOTOROLA Part III. The Hardware Interface Chapter 7. 60x Signals...

  • Page 222: Transfer Type (Tt[0Ð4])

    Timing Comments Assertion/NegationÑSame as A[0Ð31]. High ImpedanceÑSame as A[0Ð31]. 7.2.4.3 Transfer Burst (TBST) The transfer burst (TBST) signal is an input/output signal on the MPC8260. Following are the state meaning and timing comments for the TBST output/input signal. State Meaning AssertedÑIndicates that a burst transfer is in progress (see...

  • Page 223: Global (Gbl)

    Timing Comments Assertion/NegationÑSame as A[0Ð31]. 7.2.4.5 Caching-Inhibited (CI)ÑOutput The cache inhibit (CI) signal is an output signal on the MPC8260. Following are the state meaning and timing comments for CI. State Meaning AssertedÑIndicates that the transaction in progress should not be cached.

  • Page 224: Address Transfer Termination Signals

    The address transfer termination signals have no meaning in internal only mode. 7.2.5.1 Address Acknowledge (AACK) The address acknowledge (AACK) signal is an input/output on the MPC8260. 7.2.5.1.1 Address Acknowledge (AACK)ÑOutput .Following are the state meaning and timing comments for AACK as an output signal.

  • Page 225: Address Retry (Artry)

    7.2.5.2 Address Retry (ARTRY) The address retry (ARTRY) signal is both an input and output signal on the MPC8260 7.2.5.2.1 Address Retry (ARTRY)ÑOutput .Following are the state meaning and timing comments for ARTRY as an output signal. State Meaning AssertedÑIndicates that the MPC8260 detects a condition in which an address tenure must be retried.

  • Page 226: Data Bus Arbitration Signals

    The data bus grant signal (DBG) is an output/input on the MPC8260 7.2.6.1.1 Data Bus Grant (DBG)ÑInput DBG an input when MPC8260 is conÞgured to an external arbiter. The following are the state meaning and timing comments for DBG. State Meaning AssertedÑIndicates that the MPC8260 may, with the proper...

  • Page 227: Data Bus Busy (Dbb)

    7.2.6.2 Data Bus Busy (DBB) The data bus busy (DBB) signal is both an input and output signal on the MPC8260 7.2.6.2.1 Data Bus Busy (DBB)ÑOutput Following are the state meaning and timing comments for the DBB output signal. State Meaning AssertedÑIndicates that the MPC8260 is the data bus master.

  • Page 228: Data Bus (D[0Ð63])Ñoutput

    Asserted/NegatedÑRepresents the state of data during a data write. Byte lanes not selected for data transfer do not supply valid data. MPC8260 duplicates data to enable valid data to be sent to different port sizes. Timing Comments Assertion/NegationÑInitial beat coincides with DBB, for bursts,...

  • Page 229: Data Bus Parity (Dp[0Ð7])Ñinput

    Section 8.5, ÒData Tenure Operations.Ó 7.2.8.1 Transfer Acknowledge (TA) The transfer acknowledge (TA) signal is both input and output on the MPC8260. 7.2.8.1.1 Transfer Acknowledge (TA)ÑInput Following are the state meaning and timing comments for the TA input signal.

  • Page 230: Transfer Acknowledge (Ta)Ñoutput

    7.2.8.2 Transfer Error Acknowledge (TEA) The transfer error acknowledge (TEA) signal is both input and output on the MPC8260, This signal can be ignored if BCR[TEA_EN] is cleared. 7.2.8.2.1 Transfer Error Acknowledge (TEA)ÑInput Following are the state meaning and timing comments for the TEA input signal.

  • Page 231: Transfer Error Acknowledge (Tea)Ñoutput

    NegationÑOccurs one clock after assertion. 7.2.8.3 Partial Data Valid Indication (PSDVAL) The partial data valid indication (PSDVAL) is both an input and output on the MPC8260 7.2.8.3.1 Partial Data Valid (PSDVAL)ÑInput Following are the state meaning and timing comments for the PSDVAL input signal. Note that TA asserts with PSDVAL to indicate the termination of the current transfer and for each complete data beat in burst transactions.

  • Page 232: Partial Data Valid (Psdval)Ñoutput

    (Note: when the MPC8260 Processor is conÞgured for 1:1 clock mode and is performing a burst read into the data cache, the MPC8260 requires two wait state between the assertion of TS and the Þrst assertion of PSDVAL for that transaction, or 1 wait state for 1.5:1 clock mode.)

  • Page 233: The 60X Bus

    Burst A multiple-beat data transfer whose total size is typically equal to a cache block size (in MPC8260: 32 bytes, or 4 data beats at 8 bytes per beat). Cache block The PowerPC architecture deÞnes the basic unit of coherency as a cache block, which can be...

  • Page 234: Single Mpc8260 Bus Mode

    Monitoring addresses driven by a bus master to detect the need for coherency actions. Split-transaction A transaction with separate request and response tenures. Tenure The period of bus mastership. For MPC8260, there can be separate address bus tenures and data bus tenures. Transaction A complete exchange between two bus devices.

  • Page 235: 60X-Compatible Bus Mode

    Memory Control Signals Figure 8-1. Single MPC8260 Bus Mode Note that in single MPC8260 bus mode, the MPC8260 uses the address bus as a memory address bus. Slaves cannot use the 60x bus signals because the addresses have memory timing, not address tenure timing.

  • Page 236: Bus Protocol Overview

    256 bits. Four-beat burst transfers of 32-byte cache blocks require data transfer termination signals for each beat of data. Note that the MPC8260 supports port sizes of 8, 16, 32, and 64 bits and requires the additional bus signal, PSDVAL, which is not MPC8260 PowerQUICC II UserÕs Manual...

  • Page 237: Arbitration Phase

    8.3.1 Arbitration Phase The external bus design permits one device (either the MPC8260 or a bus-attached external device) to be granted bus mastership at a time. Bus arbitration can be handled either by an MOTOROLA...
  • Page 238 See Section 10.9, ÒExternal Master Support (60x-Compatible Mode),Ó for more information. The MPC8260 controls bus access through the bus request (BR) and bus grant (BG) signals. It determines the state of the address and data bus busy signals by monitoring DBG, TS, AACK, and TA, and it qualiÞes them with ABB and DBB.

  • Page 239: Address Pipelining And Split-Bus Transactions

    The arbiter asserts the internal bus grant for the highest priority request. The MPC8260 supports address bus parking through the use of the parked master bits in the arbiter conÞguration register. The MPC8260 parks the address bus (asserts the address bus grant signal in anticipation of an address bus request) to the external master or internal masters.
  • Page 240 For this case, BR is not asserted and the access latency seen by the device is shortened by one cycle. The MPC8260 and external device bus devices qualify BG by sampling ARTRY in the negated state prior to taking address bus mastership. The negation of ARTRY during the address retry window (one cycle after the assertion of AACK) indicates that no address retry is requested.

  • Page 241: Address Pipelining

    Figure 8-4. Address Bus Arbitration with External Bus Master 8.4.2 Address Pipelining The MPC8260 supports one-level address pipelining by asserting AACK to the current bus master when its data tenure starts and by granting the address bus to the next requesting device before the current data bus tenure completes.

  • Page 242: Address Transfer Attribute Signals

    The transfer type signals deÞne the nature of the transfer requested. They indicate whether the operation is an address-only transaction or whether both address and data are to be transferred. Table 8-2 describes the MPC8260Õs action as master, slave, and snooper. Table 8-2. Transfer Type Encoding 60x Bus SpeciÞcation...
  • Page 243 Burst 00110 WR w/Kill Burst 01010 Read Single-beat read or burst MOTOROLA MPC8260 as Bus Master Bus Trans. Transaction Source Address only (if sync (if enabled) enabled) Address only dcbz or dcbi (if enabled) Address only (if eieio (if enabled)
  • Page 244 Not applicable Not applicable to to MPC8260 MPC8260 Not applicable Not applicable to to MPC8260 MPC8260 MPC8260 PowerQUICC II UserÕs Manual MPC8260 as MPC8260 as Slave Snooper Action on Hit Action on Slave Hit Flush Read, assert AACK and TA.

  • Page 245: Transfer Code Signals Tc[0Ð2]

    Þrst. The MPC8260 supports critical-word-Þrst burst transactions (double-word-aligned) from the processor. The MPC8260 transfers the critical double word of data Þrst, followed by the double words from increasing addresses, wrapping back to the beginning of the eight-word block as required.

  • Page 246: Burst Ordering During Data Transfers

    8.4.3.5 Effect of Alignment on Data Transfers Table 8-6 lists the aligned transfers that can occur to and from the MPC8260. These are transfers in which the data is aligned to an address that is an integer multiple of the size of the data.
  • Page 247 As long as the attempted transfer does not cross a word boundary, the MPC8260 can transfer the data to the misaligned address within a single bus transfer (for example, a half-word read from an odd byte-aligned address). It takes two bus transfers to access data that crosses a word boundary.

  • Page 248: Effect Of Port Size On Data Transfers

    Ñ: Byte lane not used 8.4.3.6 Effect of Port Size on Data Transfers The MPC8260 can transfer operands through its 64-bit data port. If the transfer is controlled by the internal memory controller, the MPC8260 can support 8-, 16-, 32-, and 64-bit data port sizes.
  • Page 249 D[0Ð7] D[8Ð15] 8-Bit Port Size Figure 8-6. Interface to Different Port Size Devices MOTOROLA D[15Ð23] D[24Ð31] D[32Ð39] 32-Bit Port Size 16-Bit Port Size Chapter 8. The 60x Bus Part III. The Hardware Interface Interface Output Register D[40Ð47] D[48Ð55] D[56Ð63] 64-Bit Port Size...
  • Page 250 OPn: These lanes are read or written during that bus transaction. OP0 is the most-signiÞcant byte of a word operand and OP7 is the least-signiÞcant byte. Ñ Denotes a byte not required during that read cycle. Table 8-9 lists data transfer patterns for write cycles for accesses initiated by the MPC8260. 8-18 Port Size/Data Bus Assignments 64-Bit Ñ...

  • Page 251: 60X-Compatible Bus Modeñsize Calculation

    In single-MPC8260 bus mode, these calculations are internal and do not constrain the system. In 60x-compatible bus mode, the external slave or master must determine the new address and size.

  • Page 252: Extended Transfer Mode

    8-Byte 8.4.3.8 Extended Transfer Mode The MPC8260 supports an extended transfer mode that improves bus performance. This should not be confused with the extended bus protocol used to support direct-store operations supported in some earlier PowerPC processors. The MPC8260 can generate 5-, 6-, 7-, 16-, or 24-byte extended transfers.
  • Page 253 Clear BCR[ETM] to disable this type of transaction. This places the MPC8260 in strict 60x bus mode. The following tables are extensions to Table 8-9, Table 8-8, and Table 8-10.
  • Page 254 Size State [0Ð3] Address State[0Ð4] Half 3-Byte Word 5-Byte 6-Byte 7-Byte Extended transfer mode is enabled by setting the BCR[ETM]. 8-22 MPC8260 PowerQUICC II UserÕs Manual Port Size Next Size State [0Ð3] Byte Byte Half Byte Half Half Byte Byte...

  • Page 255: Address Transfer Termination

    As a bus master, the MPC8260 responds to an assertion of ARTRY by aborting the bus transaction and requesting the bus again, as shown in Figure 8-7. Note that after recognizing an assertion of ARTRY and aborting the current transaction, the MPC8260 may not run the same transaction the next time it is granted the bus.
  • Page 256 If the assertion of ARTRY is received up to or on the bus cycle after the Þrst (or only) assertion of TA for the data tenure, the MPC8260 ignores the Þrst data beat. If it is a read operation, the MPC8260 does not forward data internally to the cache, execution unit, or any other MPC8260 internal storage.
  • Page 257 During address tenures initiated by 60x-bus devices, the timing of the assertion of AACK by the MPC8260 is determined by the BCR[APD] and the pipeline status of the 60x bus. Because the MPC8260 can support one level of pipelining, it uses AACK to control the 60x-bus pipeline condition.

  • Page 258: Pipeline Control

    ARTRY (associated with the data bus operation) are negated. Note that the MPC8260 arbiter should assert DBG only when it is certain that the Þrst TA will be asserted with or after the associated ARTRY. The MPC8260 DBG is asserted with TS if the data bus is free and if the PPC_ACR[DBGD] = 0.

  • Page 259: Data Streaming Mode

    DBB is connected to the bus. This restriction is due to the fact that a MPC8260 for which data streaming mode is enabled may leave DBB asserted after the last TA of a transaction and this is a violation of the strict bus protocol. The data streaming mode is enabled by setting BCR[ETM].

  • Page 260: Effect Of Artry Assertion On Data Transfer And Arbitration

    ARTRY window (the clock after the assertion of AACK). 8.5.5 Port Size Data Bus Transfers and PSDVAL Termination The MPC8260 can transfer data via data ports of 8, 16, 32, and 64 bits, as shown in Section 8.4.3, ÒAddress Transfer Attribute Signals.Ó Single-beat transaction sizes can be 8, 16, 32, 64, 128, and 192 bits;...
  • Page 261 Figure 8-10 shows a burst transfer to a 32-bit port. Each double-word burst beat is divided into two port-sized beats such that the four double words are transferred in eight beats. MOTOROLA Chapter 8. The 60x Bus Part III. The Hardware Interface...

  • Page 262: Data Bus Termination By Assertion Of Tea

    Figure 8-10. Burst Transfer to 32-Bit Port Size 8.5.6 Data Bus Termination by Assertion of TEA If a device initiates a transaction that is not supported by the MPC8260, the MPC8260 signals an error by asserting TEA. Because the assertion of TEA is sampled by the device only during the data tenure of the bus transaction, the MPC8260 ensures that the device master receives a qualiÞed data bus grant by asserting DBG before asserting TEA.

  • Page 263: Memory Coherencyñmei Protocol

    ¥ Bus errors asserted by slaves (internal or external). 8.6 Memory CoherencyÑMEI Protocol The MPC8260 provides dedicated hardware to ensure memory coherency by snooping bus transactions, by maintaining information about the status of data in a cache block, and by the address retry capability.

  • Page 264: Processor State Signals

    Part III. The Hardware Interface When the MPC8260 processor is not the address bus master, GBL is an input. The MPC8260 processor snoops a transaction if TS and GBL are asserted together in the same bus clock cycle (a qualiÞed snooping condition). No snoop update to the MPC8260 processor cache occurs if the transaction is not marked global.

  • Page 265: Support For The Lwarx/Stwcx. Instruction Pair

    The reservation (RSRV) output signal is driven synchronously with the bus clock and reßects the status of the reservation coherency bit in the reservation address register. Note that each external master must do its own snooping; the MPC8260 does not provide external reservation snooping.
  • Page 266 Part III. The Hardware Interface 8-34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 267: Clocks And Power Control

    Þnal CPM frequency. 9.1 Clock Unit The MPC8260Õs clock module consists of the input clock interface (OSCM), the PLL, the system frequency dividers, the clock generator/driver blocks, the conÞguration control unit, and the clock control block. The clock module and the conÞguration control unit are managed through the system clock mode register (SCMR), the conÞguration bits...

  • Page 268: Clock Configuration

    33 MHz 0001_110 33 MHz 0001_111 33 MHz 0010_000 33 MHz 0010_001 33 MHz 0010_010 33 MHz MPC8260 PowerQUICC II UserÕs Manual Core Multiplication Factor Frequency 100 MHz 100 MHz 133 MHz 133 MHz 133 MHz 133 MHz 166 MHz...
  • Page 269 0100_011 0100_100 0100_101 0100_110 0100_111 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 66 MHz MOTOROLA Chapter 9. Clocks and Power Control CPM Multiplication Core Multiplication Factor Frequency 133 MHz 133 MHz 133 MHz 133 MHz 166 MHz 166 MHz 166 MHz...
  • Page 270 Because of speed dependencies, not all conÞgurations in Table 9-2 may be applicable. The 66 MHz conÞgurations are required for input clock frequencies higher than 50 MHz; 33 MHz conÞgurations are required for input clock frequencies below 50 MHz. MPC8260 PowerQUICC II UserÕs Manual CPM Multiplication Core Multiplication...

  • Page 271: External Clock Inputs

    Figure 9-1. System PLL Block Diagram The reference signal (CLKIN) goes to the phase comparator that controls the direction (up or down) that the charge pump drives the voltage across the external Þlter capacitor (XFC). MOTOROLA Chapter 9. Clocks and Power Control VCO_OUT (2*CPM_CLK) ÷...

  • Page 272: Skew Elimination

    Table 9-1. Each phase has a 50% duty cycle. 9.6 The MPC8260Õs Internal Clock Signals The internal logic of the MPC8260 uses the following internal clock lines: ¥ CPM general system clocks (CPM_CLK, CPM_CLK_90) ¥ 60x bus, core bus (BUS_CLK, BUS_CLK_90) ¥...

  • Page 273: General System Clocks

    Note that the multiplication factor ranges between 1 and 4,096. See the PLLMF Þeld description in Section 9.9, ÒSystem Clock Mode Register (SCMR).Ó Figure 9-2 shows the Þltering circuit for VCCSYN and VCCSYN1, described in Table 9-3. MOTOROLA Chapter 9. Clocks and Power Control Table 9-3. Dedicated PLL Pins...

  • Page 274: System Clock Control Register (Sccr)

    Figure 9-3. System Clock Control Register (SCCR) Table 9-4 describes SCCR Þelds. Table 9-4. SCCR Field Descriptions Defaults Bits Name Hard Reset 0Ð28 Ñ CLPD Unaffected MPC8260 PowerQUICC II UserÕs Manual VCCSYN 10 W 10 µF 0.1 µF Ñ Ñ 0x10C80 Ñ Ñ 0x10C82...

  • Page 275: System Clock Mode Register (Scmr)

    Unaffected CPM division factor. This value is always 1. 16Ð18 Ñ Ñ MOTOROLA Chapter 9. Clocks and Power Control Description Division factor of BRGCLK from VCO_OUT (twice the CPM clock). DeÞnes the BRGCLK frequency. Changing the value does not result in a loss of lock condition.

  • Page 276: Basic Power Structure

    (VCCSYN) to achieve a highly stable output frequency. The VCCSYN value is equal to the internal supply (2.0 V). The MPC8260 supports the two following power modes: ¥ Full mode: Both the chip PLL and core PLL work. ¥ Stop mode: Main PLL is working, core PLL is stopped, internal clocks are disabled.

  • Page 277: Memory Controller

    Unless stated otherwise, this chapter describes the 60x bus memory controller. The local bus memory controller provides the same functionality as the 60x bus memory controller except 64-bit port size ECC and external master support. MOTOROLA Chapter 10. Memory Controller 10-1...
  • Page 278 Part III. The Hardware Interface The MPC8260 supports the following new features as compared to the MPC860 and MPC850. ¥ The synchronous DRAM machine enables back-to-back memory read or write operations using page mode, pipelined operation and bank interleaving for high-performance systems.

  • Page 279: Features

    MPC8260 CPM/PCI 60x Address [0Ð31] 60x Data[0Ð63] Slave 60x-to-Local Transactions Local Slave CPM/Local Master Local Address [0Ð31] Local Data [0Ð63] Figure 10-1. Dual-Bus Architecture 10.1 Features The memory controllerÕs main features are as follows: ¥ Twelve memory banks Ñ 32-bit address decoding with mask Ñ...
  • Page 280 Ñ User-speciÞed control-signal patterns run when an internal or external master requests a single-beat or burst read or write access. Ñ UPM refresh timer runs a user-speciÞed control signal pattern to support refresh Ñ User-speciÞed control-signal patterns can be initiated by software 10-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 281: Basic Architecture

    Local bus access hits to 60x assigned banks are ignored. When a memory address matches BRx[BA], the corresponding machine takes ownership of the external signals that control access and maintains control until the cycle ends. MOTOROLA Chapter 10. Memory Controller Part III. The Hardware Interface 10-5...
  • Page 282 ¥ Each memory bank can be controlled by an external memory controller or bus slave. The memory controller functionality minimizes the need for glue logic in MPC8260-based systems. In Figure 10-3, CS0 is used with the 16-bit boot EPROM with BR0[MS] defaulting to select the GPCM.
  • Page 283 MPC8260 GPCM GPL1/OE BS/WE[0Ð7] UPMA Figure 10-3. Simple System Configuration Implementation differences between the supported machines are described in the following: ¥ The SDRAM machine provides a glueless interface to JEDEC-compliant SDRAM devices, and using SDRAM pipelining, page mode, and bank interleaving delivers very high performance.

  • Page 284: Address And Address Space Checking

    Note that although 60x bus accesses that hit a bank allocated to the local bus are transferred to the local bus, local bus access hits to banks allocated to the 60x bus are ignored. 60x-to-local bus transactions has priority over regular memory bank hits. 10-8 MPC8260 PowerQUICC II UserÕs Manual SDRAM Machine UPMx Signals...

  • Page 285: Page Hit Checking

    The memory controller asserts the transfer error acknowledge signal (TEA) (if enabled) in the following cases: ¥ An unaligned or burst access is attempted to internal MPC8260 space (registers or dual-port RAM). ¥ The core or an external master attempts a burst access to the local bus address space ¥...

  • Page 286: Data Buffer Controls (Bctlx)

    The MPC8260 supports the following kinds of atomic bus operations BRx[ATOM]: ¥ Read-after-write (RAWA). When a write access hits a memory bank in which ATOM = 01, the MPC8260 locks the bus for the exclusive use of the accessing master (internal or external).

  • Page 287: External Memory Controller Support

    ÒSection 4.3.2.1, ÒBus ConÞguration Register (BCR).Ó 10.2.10 External Memory Controller Support The MPC8260 has an option to allocate speciÞc banks (address spaces) to be controlled by an external memory controller or bus slave, while retaining all the bank properties: port size, data check/correction, atomic operation, and data pipelining.

  • Page 288: Partial Data Valid Indication (Psdval)

    TA is asserted when up to a double word of data is transferred. Because the MPC8260 supports memories with port sizes smaller than 64 bits, there is a need for partial data valid indication. The memory controller uses PSDVAL to indicate that data is latched by the memory on write accesses or valid data is present on read accesses.

  • Page 289: Register Descriptions

    Local bus assigned UPM refresh timer LSRT Local bus assigned SDRAM refresh timer TESCRx 60x bus error status and control registers LTESCRx Local bus error status and control regs MOTOROLA Upper 4 bytes Name Section 10.3.1 Section 10.3.2 Section 10.3.3 Section 10.3.4 Section 10.3.5...

  • Page 290: Base Registers (Brx)

    See Section 10.2.3, ÒError Checking and Correction (ECC),Ó and Section 10.2.4, ÒParity Generation and Checking.Ó 00 Data errors checking disabled 01 Normal parity checking 10 Read-modify-write parity checking 11 ECC correction and checking 10-14 MPC8260 PowerQUICC II UserÕs Manual DECC 0000_0000_0000_0000 Description EMEMC ATOM MOTOROLA...
  • Page 291 01 Read-after-write-atomic (RAWA).Writes to the address space handled by the memory controller bank cause the MPC8260 to lock the bus for the exclusive use of the master. The lock is released when the master performs a read operation from this address space. This feature is intended for CAM operations.

  • Page 292: Option Registers (Orx)

    SDAM can be read or written at any time. 0000_0000_0000 = 4Gbyte 1111_1111_1111 = 1 Mbyte Note: if xSDMR[PBI]=0, the maximum size of the memory bank should not exceed 128 Mbytes. 10-16 MPC8260 PowerQUICC II UserÕs Manual SDAM 0000_0000_0000_0000 Ñ NUMR...
  • Page 293 Page mode select. Selects page mode for the SDRAM connected to the memory controller bank. 0 Back-to-back page mode (normal operation). Page is closed when the bus becomes idle. 1 Page is kept open until a page miss or refresh occurs. MOTOROLA Description SDRAM Page Information...
  • Page 294 GPCM. This helps meet address/data hold times for slow memories and peripherals. 0 CS/WE are negated normally. 1 CS/WE are negated a quarter of a clock earlier. Note: After system reset OR0[CSNT] is set. 10-18 MPC8260 PowerQUICC II UserÕs Manual Description AM... 1111_1110_0000_0000 Ñ 1111...
  • Page 295 00 Normal timing is generated by the memory controller. No additional cycles are inserted. 01 One idle clock cycle is inserted. 10 Four idle clock cycles are inserted. 11 Eight idle clock cycles are inserted. Ñ Reserved, should be cleared. 10-19 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...
  • Page 296 01 One idle clock cycle is inserted. 10 Four idle clock cycles are inserted. 11 Eight idle clock cycles are inserted. Ñ Reserved, should be cleared. 10-20 MPC8260 PowerQUICC II UserÕs Manual 0000_0000_0000_0000 Ñ 0000_0000_0000_0000 Figure 10-9. ORxÑUPM Mode Description Ñ...

  • Page 297: Sdram Mode Register (Psdmr)

    111 Read/write (for debug purpose). 5Ð7 SDAM Address multiplex size. Determines how the address of the current memory cycle can be output on the address pins. See Section 10.4.5.1, ÒSDRAM Address Multiplexing (SDAM and BSMA).Ó MOTOROLA SDAM BSMA 0000_0000_0000_0000 0x10190 (PSDMR), 0x10194 (LSDMR)
  • Page 298 See Section 10.4.6.2, ÒActivate to Read/Write Interval.Ó ACTIVATE 001 1 clock cycle 010 2 clock cycles 111 7 clock cycles 000 8 clock cycles 10-22 MPC8260 PowerQUICC II UserÕs Manual Description For PBI = 1: 000 A10 001 A9 010 A8 011 A7...
  • Page 299 CAS latency. DeÞnes the timing for Þrst read data after SDRAM samples a column address. See Section 10.4.6.3, ÒColumn Address to First Data OutÑCAS Latency.Ó 00 Reserved 01 1 10 2 11 3 MOTOROLA Description PRECHARGE Chapter 10. Memory Controller Part III. The Hardware Interface command after the last...

  • Page 300: Local Bus Sdram Mode Register (Lsdmr)

    See Section 10.4.5.1, ÒSDRAM Address Multiplexing (SDAM and BSMA).Ó 8Ð10 BSMA Bank select multiplexed address line. Selects which MPC8260 address pins serve as bank-select address for the local bus SDRAM. See Section 10.4.5.1, ÒSDRAM Address Multiplexing (SDAM and BSMA).Ó...
  • Page 301 SDRAM. See Section 10.4.6.5, ÒLast Data In to PrechargeÑWrite Recovery.Ó 01 1 clock cycles 10 2 clock cycles 11 3 clock cycles 00 4 clock cycles MOTOROLA Description SDRAM DeviceÐSpeciÞc Parameters: PRECHARGE Chapter 10. Memory Controller Part III. The Hardware Interface...

  • Page 302: Machine A/B/C Mode Registers (Mxmr)

    Addr 0x10170 (MAMR); 0x10174 (MBMR); 0x10178 (MCMR) Field RLFx WLFx Reset Addr 0x10172 (MAMR); 0x10176 (MBMR); 0x1017A (MCMR) Figure 10-11. Machine x Mode Registers (MxMR) 10-26 MPC8260 PowerQUICC II UserÕs Manual Description Ñ 0000_0000_0000_0 TLFx 0000_0000_0000_0000 ACTIVATE G0CLx GPL_x4DIS RLFx...
  • Page 303 The address output on the pins controlled by the contents of the UPMx RAM array. This Þeld is useful when connecting the MPC8260 to DRAM devices requiring row and column addresses multiplexed on the same pins.

  • Page 304: Memory Data Register (Mdr)

    The memory data register (MDR), shown in Figure 10-12, contains data written to or read from the RAM array for UPM issuing a write command to the UPM. 10-28 MPC8260 PowerQUICC II UserÕs Manual Description commands. MDR must be set up before READ...

  • Page 305: Memory Address Register (Mar)

    UPM. 10.3.7 Memory Address Register (MAR) The memory address register (MAR) is shown in Figure 10-13. Field Reset Addr Field Reset Addr Figure 10-13. Memory Address Register (MAR) MOTOROLA 0000_0000_0000_0000 0x10188 0000_0000_0000_0000 0x1018A Description 0000_0000_0000_0000 0x10168 0000_0000_0000_0000 0x10116A Chapter 10.

  • Page 306: Bus-Assigned Upm Refresh Timer (Purt)

    10.3.9 Local Bus-Assigned UPM Refresh Timer (LURT) The local bus assigned UPM refresh timer register (LURT) is shown in Figure 10-15. Field Reset Addr Figure 10-15. Local Bus-Assigned UPM Refresh Timer (LURT) 10-30 MPC8260 PowerQUICC II UserÕs Manual Description PURT 0000_0000 0x10198 Description æ...

  • Page 307: Bus-Assigned Sdram Refresh Timer (Psrt)

    Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given MPTPR[PTP] = 32, the PSRT value should be 12 decimal. 12/(25 MHz/32) = 15.36 µs, which is less than the required service period of 15.6 µs. MOTOROLA Description æ...

  • Page 308: Local Bus-Assigned Sdram Refresh Timer (Lsrt)

    Name 0Ð7 Refresh timers prescaler. Determines the period of the memory refresh timers input clock. It divides the system clock. 8Ð15 Ñ Reserved, should be cleared 10-32 MPC8260 PowerQUICC II UserÕs Manual LSRT 0000_0000 0x101A4 Description æ LSRT ö ---------------- - è...

  • Page 309: Bus Error Status And Control Registers (Tescrx)

    (L_TESCR1),Ó and Section 4.3.2.13, ÒLocal Bus Transfer Error Status and Control Register 2 (L_TESCR2).Ó 10.4 SDRAM Machine The MPC8260 provides one SDRAM interface (machine) for the 60x bus and one for the local bus. The machines provide the necessary control functions and signals for JEDEC-compliant SDRAM devices.
  • Page 310 A[17] PSDA10 12-bit A[19Ð28] D[0Ð63] CS[0Ð7] PSDRAS PSDWE PSDCAS Figure 10-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown) 10-34 MPC8260 PowerQUICC II UserÕs Manual 2x1M x8 SDRAM ADDR[0Ð11] DQ[0Ð7] DATA[0Ð7] 2x1M x8 SDRAM ADDR[0Ð11] DQ[0Ð7] DATA[0Ð7] 2x1M x8 SDRAM ADDR[0Ð11]...

  • Page 311: Sdram Power-On Initialization

    1, 2, 3, or 4, etc.). Burst type must be chosen according to the 60x cache wrap (sequential). Although some SDRAMs provide burst lengths of 1, 2, 4, 8, or a page, MPC8260 supports only a 4-beat burst for 64-bit port size and an 8-beat burst for 32-bit port size. MPC8260 does not support burst lengths of 1, 2, and a page for SDRAMs.

  • Page 312: Page-Mode Support And Pipeline Accesses

    Restores data from the sense ampliÞers to the appropriate row. Also initializes the sense ampliÞers to PRECHARGE prepare for reading another row in the SDRAM array. A SINGLE BANK read or write if the row address changes on the next access. Note that the MPC8260 uses the SDA10 ALL BANKS pin to distinguish the format.

  • Page 313: Sdram Address Multiplexing (Sdam And Bsma)

    ConÞguration Examples.Ó 10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA) In single MPC8260 mode, the lower bits of the address bus are connected to the deviceÕs address port, and the memory controller multiplex the row/column and the internal banks select lines, according to the PL/SDMR[SDAM] and PL/SDMR[BSMA].

  • Page 314: Precharge-To-Activate Interval

    10-38 MPC8260 PowerQUICC II UserÕs Manual A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22...

  • Page 315: Activate To Read/Write Interval

    This parameter, controlled by P/LSDMR[ACTTORW], deÞnes the earliest timing for command after an READ WRITE SDRAS SDCAS MA[0Ð11] DATA ACTTORW = 2 ACTIVATE Command Command Figure 10-21. ACTTORW = 2 (2 Clock Cycles) MOTOROLA command. ACTIVATE WRITE Chapter 10. Memory Controller Part III. The Hardware Interface 10-39...

  • Page 316: Column Address To First Data Outñcas Latency

    PRECHARGE the CL parameter. Activate SDRAS SDCAS MA[0Ð11] Data Figure 10-23. LDOTOPRE = 2 (-2 Clock Cycles) 10-40 MPC8260 PowerQUICC II UserÕs Manual Read First data out CL = 2 Column Read Deactivate LDOTOPRE = 2 Column Last Data Out...

  • Page 317: Last Data In To Prechargeñwrite Recovery

    Figure 10-25. RFRC = 4 (6 Clock Cycles) 10.4.6.7 External Address Multiplexing Signal In 60x-compatible mode, external address multiplexing is placed on the address lines. If the additional delay of multiplexing is endangers the device setup time, P/LSDMR[EAMUX] MOTOROLA WRITE Last data in WRC = 2 Column command.

  • Page 318: External Address And Command Buffers (Bufcmd)

    Activate (without cs) MA[0Ð11] Command setup cycle 10.4.7 SDRAM Interface Timing The following Þgures show SDRAM timing for various types of accesses. 10-42 MPC8260 PowerQUICC II UserÕs Manual Read Column Figure 10-26. EAMUX = 1 Read Column Command setup cycle Figure 10-27.
  • Page 319 Data Figure 10-29. SDRAM Single-Beat Read, Page Hit, CL = 3 SDRAS SDCAS MA[0Ð11] Data Figure 10-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3 MOTOROLA Column Column Column Chapter 10. Memory Controller Part III. The Hardware Interface 10-43...
  • Page 320 Figure 10-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3 SDRAS SDCAS MA[0Ð11] Data Figure 10-32. SDRAM Single-Beat Write, Page Hit SDRAS SDCAS MA[0Ð11] Data Figure 10-33. SDRAM Three-Beat Burst Write, Page Closed 10-44 MPC8260 PowerQUICC II UserÕs Manual Activate Column Column MOTOROLA...
  • Page 321 Figure 10-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 SDRAS SDCAS MA[0Ð11] Data Figure 10-35. SDRAM Write-after-Write Pipelined, Page Hit SDRAS SDCAS MA[0Ð11] Data Figure 10-36. SDRAM Read-after-Write Pipelined, Page Hit MOTOROLA Column1 Column2 Column1 Column1 Chapter 10. Memory Controller Part III. The Hardware Interface Column2 Column2 10-45...

  • Page 322: Sdram Read/Write Transactions

    For writes that require less than the full burst length, the MPC8260 protects non-targeted addresses by driving DQMn high on the irrelevant cycles of the burst. However, system performance is not compromised since, if a new transaction is pending, the MPC8260 begins executing it immediately, effectively terminating the burst early.

  • Page 323: Sdram Refresh

    P/LSRT depends on the speciÞc SDRAM devices used and the operating frequency of the MPC8260Õs bus. This value should allow for a potential collision between memory accesses and refresh cycles. The period of the refresh interval must be greater than the access time to ensure that read and write operations complete successfully.
  • Page 324 The following parameters can be extracted: ¥ PSDMR[PBI] = 1ÑPage-based interleaving ¥ ORx[BPD] = 01ÑFour internal banks ¥ ORx[ROWST] = 0110ÑRow starts at A[6] ¥ ORx[NUMR] = 011ÑTwelve row lines 10-48 MPC8260 PowerQUICC II UserÕs Manual RFRC A[6Ð17] A[18Ð19] Bank select Activate A[20Ð28]...
  • Page 325 Table 10-24. Register Settings (Page-Based Interleaving Register DECC LSDAM ROWST PSDMR RFEN SDAM BSMA SDA10 RFRC PRETOACT MOTOROLA ACTIVATE A[15Ð16] A[17] A[18] A[19] DonÕt care DonÕt care command and AP during ACTIVATE Settings Base address EMEMC...
  • Page 326 A[9] on the SDA10 line during the ACTIVATE command and AP during READ/WRITE and CBR commands. Table 10-28 shows the register conÞguration. Not shown are PSRT and MPTPR, which should be programmed according to the device refresh requirements. 10-50 MPC8260 PowerQUICC II UserÕs Manual A[6Ð7] A[8Ð19] A[15Ð16] Internal bank select (A[6Ð7])

  • Page 327: General-Purpose Chip-Select Machine (Gpcm)

    Users familiar with the MPC8xx memory controller should read Section 10.5.4, ÒDifferences between MPC8xxÕs GPCM and MPC8260Õs GPCM,Ó Þrst. The GPCM allows a glueless and ßexible interface between the MPC8260, SRAM, EPROM, FEPROM, ROM devices, and external peripherals. The GPCM contains two basic conÞguration register groupsÑBRx and ORx.
  • Page 328 Write (1+1/2)*Clock Write Write (1+1/4)*Clock Write (1+1/2)*Clock SCY is the number of wait cycles from the option register. 10-52 MPC8260 PowerQUICC II UserÕs Manual 32-Bit Wide SRAM WE[0–3] Address Data Signal Behavior CS Negated to Address Change Address/Data Invalid -1/4*Clock...

  • Page 329: Chip-Select Assertion Timing

    ¥ One quarter of a clock cycle later ¥ One half of a clock cycle later Figure 10-41 shows a basic connection between the MPC8260 and an external peripheral device. Here, CS (the strobe output for the memory access) is connected directly to CE of the memory device and BCTL0 is connected to the respective R/W in the peripheral device.

  • Page 330: Chip-Select And Write Enable Deassertion Timing

    Part III. The Hardware Interface 10.5.1.2 Chip-Select and Write Enable Deassertion Timing Figure 10-43 shows a basic connection between the MPC8260 and a static memory device. Here, CS is connected directly to CE of the memory device. The WE signals are connected to the respective W signal in the memory device where each WE corresponds to a different data byte.

  • Page 331: Relaxed Timing

    ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. When TRLX = 1 and ACS ¹ 00, an additional cycle between the address and strobes is inserted by the MPC8260 memory controller. See Figure 10-46 and Figure 10-47.
  • Page 332 Clock Address PSDVAL Data Figure 10-48 GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1) 10-56 MPC8260 PowerQUICC II UserÕs Manual ACS = 10 ACS = 11 CSNT = 1 ACS = 10 MOTOROLA...

  • Page 333: Output Enable (Oe) Timing

    ORx[29Ð30] (TRLX and EHTR). Any access following a read access to the slower memory bank is delayed by the number of clock cycles speciÞed by Table 10-31. See Figure 10-50 through Figure 10-53 for timing examples. MOTOROLA Chapter 10. Memory Controller 10-57...
  • Page 334 Table 10-31. TRLX and EHTR Combinations ORx[TRLX] ORx[EHTR] Figure 10-50 through Figure 10-53 show timing examples. Clock Address PSDVAL Data Figure 10-50. GPCM Read Followed by Read (ORx[29Ð30] = 0x, Fastest Timing) 10-58 MPC8260 PowerQUICC II UserÕs Manual Number of Hold Time Clock Cycles MOTOROLA...
  • Page 335 Figure 10-51. GPCM Read Followed by Read (ORx[29Ð30] = 01) Clock Address PSDVAL Data Figure 10-52. GPCM Read Followed by Write (ORx[29Ð30] = 01) MOTOROLA Hold Time 1-cycle hold time allowed Hold Time Long hold time allowed Chapter 10. Memory Controller Part III.

  • Page 336: External Access Termination

    External access termination is supported by the GPCM using GTA, which is synchronized and sampled internally by the MPC8260. If, during a GPCM data phase (second cycle or later), the sampled signal is asserted, it is converted to PSDVAL, which terminates the current GPCM access.

  • Page 337: Boot Chip-Select Operation

    The CS0 signal is the boot chip-select output; its operation differs from the other external chip-select outputs on system reset. When the MPC8260 internal core begins accessing memory at system reset, CS0 is asserted for every address in the boot address range, unless an internal register is accessed.

  • Page 338: Differences Between Mpc8Xxõs Gpcm And Mpc8260Õs Gpcm

    TA and so must be asserted in sync with the system clock. In the MPC8260, this signal is separated from the bus and named GTA. The signal is synchronized internally and sampled. The sampled signal is used to generate TA, which terminates the bus transaction.
  • Page 339 When an address match is found in one of the memory banks, BRx[MS] selects the UPM to handle this memory access. MxMR[BS] assigns the UPM to the 60x or the local bus. MOTOROLA Array Index Index...

  • Page 340: Requests

    RAM words. Read Single-Beat Request Read Burst Request Write Single-Beat Request Write Burst Request Refresh Timer Request Exception Condition Request Figure 10-56. RAM Array Indexing 10-64 MPC8260 PowerQUICC II UserÕs Manual Array Index Generator RAM Array 64 RAM Words MOTOROLA...

  • Page 341: Memory Access Requests

    8 data acknowledges; an 8-bit device requires 32. See Section 10.2.13, ÒPartial Data Valid Indication (PSDVAL).Ó The MPC8260 deÞnes two additional transfer sizes: bursts of two and three doublewords. These access are treated by the UPM as back-to-back, single-beat transfers.

  • Page 342: Exception Requests

    Table 10-35), otherwise bus timeout may occur. 10.6.1.4 Exception Requests When the MPC8260 under UPM control initiates an access to a memory device, the external device may assert TEA or SRESET. The UPM provides a mechanism by which memory control signals can meet the timing requirements of the device without losing data.

  • Page 343: Clock Timing

    If speciÞed in the RAM, the value of the external signals can be changed after any of the positive edges of T[1Ð4], plus a circuit delay time as speciÞed in the MPC8260 Hardware SpeciÞcations.
  • Page 344 The state of the external signals may change (if speciÞed in the RAM array) at any positive edge of T1, T2, T3, or T4 (there is a propagation delay speciÞed in the MPC8260 Hardware SpeciÞcations). Note however that only the CS signal corresponding to the currently accessed bank is manipulated by the UPM pattern when it runs.

  • Page 345: The Ram Array

    Figure 10-61. The signals at the bottom of Figure 10-61 are UPM outputs. The selected CS is for the bank that matches the current address. The selected BS is for the byte lanes read or written by the access. MOTOROLA CST3 CST4...

  • Page 346: Ram Words

    Ñ (MCR[MAD] indirect addressing of 1 of 64 entries G5T1 G5T3 REDO LOOP EXEN Ñ Figure 10-62. The RAM Word MPC8260 PowerQUICC II UserÕs Manual TSIZ, PS, A[30,31] Byte Select Packaging 10 11 G1T1 G1T3 G2T1 G2T3 26 27 TODT LAST...
  • Page 347 10 The value of the GPL0 line at the rising edge of T3 will be 0 11 The value of the GPL0 line at the rising edge of T3 will be 1 See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó MOTOROLA Description Chapter 10. Memory Controller Part III.
  • Page 348 WAEN If MxMR[GPLx4DIS] = 1, WAEN is selected. See Section 10.6.4.5, ÒThe Wait Mechanism.Ó 0 The UPWAITx function is disabled. 1 A freeze in the external signals logical value occurs if the external WAIT signal is detected asserted. This condition lasts until WAIT is negated. 10-72 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...
  • Page 349 TEA or SRESET. An exception occurs when one of these signals is asserted by an external device and the MPC8260 begins closing the memory cycle transfer. When one of these exceptions is recognized and EXEN in the RAM word is set, the UPM branches to the special exception start address (EXS) and begins operating as the pattern deÞned there speciÞes.

  • Page 350: Chip-Select Signals (Cxtx)

    CSx signal of the corresponding bank depends on the value of each CSTn bit. Figure 10-63 and the timing diagrams in Figure 10-60 show how UPMs control CS signals. 10-74 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 351: Byte-Select Signals (Bxtx)

    BS3 indicates that D[24Ð31] contains valid data during a cycle, and so forth. Table 10-31 shows how BS signals affect 64-, 32-, 16-, and 8-bit accesses. Note that for a refresh timer request, all the BS signals are asserted/negated by the UPM. MOTOROLA Bank Selected Switch MS[0–1] in BRx...

  • Page 352: General-Purpose Signals (Gxtx, Gox)

    ¥ When LOOP and REDO are set together, the loop mechanism works as usual and the line is repeated according to the REDO function. ¥ LAST and REDO should not be set together. ¥ REDO should not be used within the exception routine. 10-76 MPC8260 PowerQUICC II UserÕs Manual Loop Field RLFx RLFx WLFx...

  • Page 353: Address Multiplexing

    CLKIN instead of the rising edge. The data is sampled by the internal master on the next rising edge as is required by the MPC8260 bus operation spec. This feature lets the user speed up the memory interface by latching data 1/2 clock early, which can be useful during burst reads.

  • Page 354: Signals Negation

    Figure 10-66 shows, the CSx and GPL1 states (C12 and F) and the WAEN value (C) are frozen until UPWAIT is recognized as deasserted. WAEN is typically set before the line that contain UTA = 1. 10-78 MPC8260 PowerQUICC II UserÕs Manual CLKIN Data Bus MOTOROLA...

  • Page 355: Extended Hold Time On Read Accesses

    10.6.5 UPM DRAM ConÞguration Example Consider the following DRAM organization: ¥ 64-bit port size organized as 8 x 8 x 16 Mbits ¥ Each device has 12 row lines and 9 column lines. MOTOROLA c9 c10 c11 Word n+2 Wait Masters Chapter 10.

  • Page 356: Differences Between Mpc8Xx Upm And Mpc8260 Upm

    Users familiar with the MPC8xx UPM should read this section Þrst. Below is a list of the major differences between the MPC8xx devices and the MPC8260: ¥ First cycle timing transferred to the UPM arrayÑIn the MPC8xxÕs UPM, the Þrst cycle value of some of the signals is determined from ORx[SAM,G5LA,G5LS].

  • Page 357: Memory System Interface Example Using Upm

    ¥ Timing of GPL[0Ð5]ÑIn the MPC8xxÕs UPM, the GPL lines could change on the positive edge of T2 or T3. In the MPC8260 these signals can change in the positive edge of T1 or T3 to allow connection to high-speed synchronous devices such as burst SRAM.
  • Page 358 DRAM device used. The MS Þeld should indicate the speciÞc UPM selected to handle the cycle. The RAM array of the UPM can than be written through use of the 10-82 MPC8260 PowerQUICC II UserÕs Manual 1M x 16 CAS[0–1] CAS[0–1]...
  • Page 359 RSS+1 Figure 10-68. Single-Beat Read Access to FPM DRAM MOTOROLA RSS+2 Chapter 10. Memory Controller Part III. The Hardware Interface Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5...
  • Page 360 WSS+1 Figure 10-69. Single-Beat Write Access to FPM DRAM 10-84 MPC8260 PowerQUICC II UserÕs Manual WSS+2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8...
  • Page 361 RBS+1 Figure 10-70. Burst Read Access to FPM DRAM (No LOOP) MOTOROLA Column 2 Column 3 RBS+2 RBS+3 RBS+4 RBS+5 Chapter 10. Memory Controller Part III. The Hardware Interface Column 4 Bit 0...
  • Page 362 RBS+1 Figure 10-71. Burst Read Access to FPM DRAM (LOOP) 10-86 MPC8260 PowerQUICC II UserÕs Manual Column 2 Column 3 RBS+2 RBS+3 RBS+4 Column 4 Bit 0 Bit 1 Bit 2 Bit 3...
  • Page 363 WBS+1 Figure 10-72. Burst Write Access to FPM DRAM (No LOOP) MOTOROLA Column 2 Column 3 WBS+2 WBS+3 WBS+4 WBS+5 Chapter 10. Memory Controller Part III. The Hardware Interface Column 4 Bit 0...
  • Page 364 PTS+1 Figure 10-73. Refresh Cycle (CBR) to FPM DRAM 10-88 MPC8260 PowerQUICC II UserÕs Manual PTS+2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8...
  • Page 365 MOTOROLA Figure 10-74. Exception Cycle Chapter 10. Memory Controller Part III. The Hardware Interface Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7...
  • Page 366 Select between GPL4 and Wait = Wait, data sampled at clock negative edge Burst inhibit device The timing diagram in Figure 10-75 shows how the burst-read access shown in Figure 10-70 can be reduced. 10-90 MPC8260 PowerQUICC II UserÕs Manual Field Value BRx[MS] 0b100...
  • Page 367 RBS+1 Figure 10-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of MOTOROLA col 2 col 3 col 4 RBS+2 RBS+3 RBS+4 RBS+5 CLKIN) Chapter 10. Memory Controller Part III. The Hardware Interface...

  • Page 368: Edo Interface Example

    D[0Ð63] GPL1 Figure 10-76. MPC8260/EDO Interface Connection to the 60x Bus Table 10-43 shows the programming of the register Þeld for supporting the conÞguration shown in Figure 10-76. The example assumes a CLKIN frequency of 66 MHz and that the device needs a 1,024-cycle refresh every 10 µs.
  • Page 369 RSS+1 Figure 10-77. Single-Beat Read Access to EDO DRAM MOTOROLA RSS+2 RSS+3 RSS+4 Chapter 10. Memory Controller Part III. The Hardware Interface Bit 0 Bit 1 Bit 2 Bit 3 Bit 4...
  • Page 370 WSS+1 Figure 10-78. Single-Beat Write Access to EDO DRAM 10-94 MPC8260 PowerQUICC II UserÕs Manual WSS+2 WSS+3 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7...

  • Page 371: Wait States

    WSS+1 Figure 10-79. Single-Beat Write Access to EDO DRAM Using REDO to Insert Three MOTOROLA WSS+2 REDO1 REDO2 REDO3 Wait States Chapter 10. Memory Controller Part III. The Hardware Interface Bit 0 Bit 1...
  • Page 372 RBS+1 RBS+2 Figure 10-80. Burst Read Access to EDO DRAM 10-96 MPC8260 PowerQUICC II UserÕs Manual Column 2 Column 3 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 Column 4 Bit 0 Bit 1 Bit 2...
  • Page 373 WBS+1 WBS+2 Figure 10-81. Burst Write Access to EDO DRAM MOTOROLA Column 2 Column 3 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 Chapter 10. Memory Controller Part III. The Hardware Interface Column 4 Bit 0...
  • Page 374 PTS+1 Figure 10-82. Refresh Cycle (CBR) to EDO DRAM 10-98 MPC8260 PowerQUICC II UserÕs Manual PTS+2 PTS+3 PTS+4 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6...
  • Page 375 Figure 10-83. Exception Cycle For EDO DRAM MOTOROLA Chapter 10. Memory Controller Part III. The Hardware Interface Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6...

  • Page 376: Handling Devices With Slow Or Variable Access Times

    ¥ The external termination solution (GPCM)ÑThe core generates a read access from the slow device, which must generate the asynchronous GTA when it is ready. 10-100 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 377: External Master Support (60X-Compatible Mode)

    CPM are considered internal; accesses from an external bus master are external. External bus master support is available only if the MPC8260 is placed in 60x-compatible mode. This is done by setting the BCR[EBM], described in Section 4.3.2.1, ÒBus ConÞguration Register (BCR).Ó...

  • Page 378: Using Bnksel Signals In Single-Mpc8260 Bus Mode

    SDRAMs that have different numbers of row or column address lines. The address lines of the MPC8260 bus and the BNKSEL lines can be routed independently to the address lines and BA lines of the DIMM. Note that all SDRAMs populated on an MPC8260 bus must still have the same organization.
  • Page 379 ALE only on the start of new memory controller access. Figure 10-84 shows the pipelined bus operation in 60x-compatible mode. CLKIN ADDR + ATTR AACK PSDVAL BADDR[27–28] Figure 10-84. Pipelined Bus Operation and Memory Access in 60x-Compatible MOTOROLA Mode Chapter 10. Memory Controller Part III. The Hardware Interface 10-103...

  • Page 380: Example Of External Master Using The Sdram Machine

    Figure 10-86 shows an interconnection in which a 60x-compatible external master and the MPC8260 can share access to a SDRAM bank. Note that the address multiplexer is controlled by SDAMUX, while the address latch is controlled by ALE. Also note that because this is a 64-bit port size SDRAM, BADDR is not needed.
  • Page 381 BNKSEL,SDWE,SDRAS,SDCAS DQM[0–7] SDAMUX MPC8260 TSIZ[1–3] TSIZ[0] PSDVAL Figure 10-86. External Master Configuration with SDRAM Device MOTOROLA SDRAM 64-Bit Port Size Multiplexer Latch A[0–31] D[0–63] TT[0–4] TBST (pull down) (pull up) Arbitration signals Chapter 10. Memory Controller Part III. The Hardware Interface External Master TSIZ[0–2]...
  • Page 382 Part III. The Hardware Interface 10-106 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 383: Secondary (L2) Cache Support

    Copy-back mode requires that the L2 cache is able to initiate copy-backs to main memory. To do this, the L2 cache must act as a bus master and implement the bus arbitration signals BR, BG, and DBG. The MPC8260 can also support additional bus masters (60x or MPC8260 type) in copy-back mode.

  • Page 384: Write-Through Mode

    In write-through mode, cacheable read operations that hit in the L2 cache are serviced from the L2 cache without requiring a memory transaction and its associated latency. Thus, reads 11-2 MPC8260 PowerQUICC II UserÕs Manual (pull up) (pull down) Latch...
  • Page 385 MPC8260 required in write-through mode. The MPC8260 can also support additional bus masters (60x or MPC8260 type) in write-through mode. Figure 11-2 shows a MPC8260 connected to a MPC2605 integrated L2 cache in write- through mode. MOTOROLA Chapter 11.

  • Page 386: Ecc/Parity Mode

    ECC/parity mode is a subset of write-through mode with some connection changes that allow the L2 cache to support ECC or Parity. The connection changes are: ¥ The MPC8260Õs DP[0:7] signals are connected to the L2 cacheÕs DP[0:7] signals. ¥ The L2Õs TSIZ[0:2] signals are pulled down to always indicate 8-byte transaction size.
  • Page 387 ¥ Only MPC8260-type masters are supported in systems that use ECC/parity L2 cache mode. See Section 10.9, ÒExternal Master Support (60x-Compatible Mode),Ó for more information about external master types. Figure 11-3 shows a MPC8260 connected to an MPC2605 integrated L2 cache in ECC/ Parity mode. MOTOROLA Chapter 11.
  • Page 388 CI, GBL, TA, DBB, TEA AACK, ARTRY TSIZE[0] L2_HIT A[0Ð31] D[0Ð63],DP[0Ð7] Memory Controller Figure 11-3. External L2 Cache in ECC/Parity Mode 11-6 MPC8260 PowerQUICC II UserÕs Manual (pull up) (pull up) (pull downs) (pull down) (pull down) (pull downs) Latch SDRAM Main Memory...

  • Page 389: L2 Cache Interface Parameters

    11.4 L2 Cache Operation When conÞgured for an L2 cache (BCR[L2C] = 1), the MPC8260 samples the L2_HIT input signal when the delay time programmed in BCR[L2D] expires. For 60x bus cycles, if L2_HIT is asserted, the external L2 cache drives AACK and TA to complete the transaction without the MPC8260 initiating a system memory transfer.

  • Page 390: Timing Example

    Figure 11-4 shows a read access performed by the MPC8260 with an externally controlled L2 cache. For the Þrst transaction (A0), the MPC8260 grants the bus and asserts TS with the address and address transfer attributes. In this example, BCR[L2D] = 0, which means that L2_HIT is valid one clock cycle after the assertion of TS.
  • Page 391 Part III. The Hardware Interface Addr A0 & TBST& CI A1 & TBST disabled active Memc controls AACK MPC8260 DATA L2D = 0 L2 HIT Figure 11-4. Read Access with L2 Cache MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-9...
  • Page 392 Part III. The Hardware Interface 11-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 393: Ieee 1149.1 Test Access Port

    Chapter 12 IEEE 1149.1 Test Access Port The MPC8260 provides a dedicated user-accessible test access port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG).

  • Page 394: Tap Controller

    The value shown adjacent to each bubble represents the value of the TMS signal sampled on the rising edge of the TCK signal. Figure 12-2 shows the state machine. 12-2 MPC8260 PowerQUICC II UserÕs Manual Boundary Scan Register Bypass Instruction Apply & Decode Register 4ÐBit Instruction Register...

  • Page 395: Boundary Scan Register

    EXTAL, and XFC pins are associated with analog signals and are not included in the boundary scan register. An IEEE-1149.1-compliant boundary-scan register has been included on the MPC8260 that can be connected between TDI and TDO when EXTEST or SAMPLE/PRELOAD instructions are selected. It is used for capturing signal pin data on the input pins, forcing Þxed values on the output signal pins, and selecting the direction and...
  • Page 396 Figure 12-3. Output Pin Cell (O.Pin) To Next Cell Data to System Logic Figure 12-4. Observe-Only Input Pin Cell (I.Obs) 12-4 MPC8260 PowerQUICC II UserÕs Manual Shift DR To Next Cell Clock DR Update DR Clock DR From Last Cell...
  • Page 397 The shift register cell nearest TDO (Þrst to be shifted in) is deÞned as Bit 1 and the last bit to be shifted in is bit 475. The second column references one of the three MPC8260Õs cell types depicted in Figure 12-3 through Figure 12-5 that describe the cell structure for each MOTOROLA Chapter 12.
  • Page 398 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin 12-6 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type pa[4] pa[4] g2.ctl Ñ spare5 spare5 g287.ctl Ñ pa[5] pa[5] g286.ctl Ñ pd[8] pd[8] g285.ctl...
  • Page 399 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Part III. The Hardware Interface Pin/Cell Name Pin Type g277.ctl Ñ pb[10] pb[10] g276.ctl Ñ pa[8] pa[8] g275.ctl Ñ...
  • Page 400 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin 12-8 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type g263.ctl Ñ pb[13] pb[13] g262.ctl Ñ pa[12] pa[12] g261.ctl Ñ pd[14] pd[14] g260.ctl Ñ...
  • Page 401 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Part III. The Hardware Interface Pin/Cell Name Pin Type g250.ctl Ñ pc[13] pc[13] g249.ctl Ñ pb[16] pb[16] g248.ctl Ñ...
  • Page 402 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin 12-10 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type g237.ctl Ñ pb[23] pb[23] g236.ctl Ñ pa[19] pa[19] g235.ctl Ñ pc[17] pc[17] g234.ctl Ñ...
  • Page 403 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Part III. The Hardware Interface Pin/Cell Name Pin Type g224.ctl Ñ pb[20] pb[20] g223.ctl Ñ pa[22] pa[22] g222.ctl Ñ...
  • Page 404 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs i.obs o.pin IO.ctl i.obs 12-12 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type g212.ctl Ñ pc[24] pc[24] g211.ctl Ñ pb[25] pb[25] g210.ctl Ñ pa[25] pa[25] g209.ctl Ñ...
  • Page 405 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Part III. The Hardware Interface Pin/Cell Name Pin Type sreset_b g170.ctl Ñ clkin pc[27] pc[27] g166.ctl Ñ pd[28] pd[28] g165.ctl...
  • Page 406 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin 12-14 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type pa[30] pa[30] g154.ctl pd[31] pd[31] g153.ctl pc[31] pc[31] g152.ctl pb[31] pb[31] g151.ctl pa[31] pa[31] g150.ctl...
  • Page 407 IO.ctl o.pin i.obs o.pin i.obs o.pin i.obs o.pin i.obs o.pin i.obs o.pin MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Pin/Cell Name Pin Type g89.ctl psdval_b psdval_b g130.ctl dbb_b_irq3_b dbb_b_irq3_b g129.ctl dbg_b dbg_b g128.ctl spare4 spare4 g127.ctl...
  • Page 408 IO.ctl i.obs o.pin i.obs o.pin 12-16 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type g111.ctl Ñ a[26] a[26] a[25] a[25] a[24] a[24] a[23] a[23] a[22] a[22] a[21] a[21]...
  • Page 409 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Part III. The Hardware Interface Pin/Cell Name Pin Type a[8] a[8] a[7] a[7] a[6] a[6] a[5] a[5] a[4]...
  • Page 410 IO.ctl i.obs o.pin i.obs o.pin i.obs o.pin i.obs o.pin 12-18 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type bg_b bg_b g115.ctl irq7_b_int_out_b_ape_b irq7_b_int_out_b_ape_b g114.ctl ts_b ts_b tsize[3] tsize[3] tsize[2] tsize[2] g113.ctl tsize[1]...
  • Page 411 IO.ctl i.obs o.pin i.obs o.pin i.obs o.pin i.obs o.pin i.obs o.pin i.obs o.pin i.obs MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Part III. The Hardware Interface Pin/Cell Name Pin Type d[54] d[54] d[46] d[46] d[38] d[38] d[30] d[30] g106.ctl Ñ...
  • Page 412 IO.ctl i.obs 12-20 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type d[36] d[28] d[28] g104.ctl Ñ d[20] d[20] d[12] d[12] d[4] d[4] d[59] d[59] d[51]...
  • Page 413 IO.ctl i.obs o.pin i.obs o.pin i.obs o.pin MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Part III. The Hardware Interface Pin/Cell Name Pin Type d[18] d[10] d[10] d[2] d[2] d[57] d[57] d[49] d[49]...
  • Page 414 IO.ctl i.obs o.pin IO.ctl o.pin i.obs o.pin IO.ctl o.pin o.pin o.pin o.pin o.pin o.pin o.pin o.pin 12-22 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type dp7_cse1_irq7_b dp7_cse1_irq7_b g99.ctl dp6_cse0_irq6_b dp6_cse0_irq6_b g98.ctl dp5_tben_irq5_b dp5_tben_irq5_b g97.ctl dp4_irq4_b dp4_irq4_b g96.ctl dp3_irq3_b dp3_irq3_b g95.ctl...
  • Page 415 IO.ctl i.obs o.pin IO.ctl o.pin o.pin o.pin o.pin i.obs o.pin i.obs o.pin IO.ctl MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Pin/Cell Name Pin Type we_dqm_bs_b[3] we_dqm_bs_b[2] we_dqm_bs_b[1] bctl0_b we_dqm_bs_b[0] lsdamux_gpl5 lgta_b_upwait_gpl4_pbs lgta_b_upwait_gpl4_pbs g66.ctl lsdcas_b_gpl3 loe_b_sdras_b_gpl2 lsdwe_b_gpl1...
  • Page 416 IO.ctl i.obs o.pin i.obs o.pin i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin 12-24 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type lcl_d_ad[4] lcl_d_ad[4] lcl_d_ad[3] lcl_d_ad[3] lcl_d_ad[2] lcl_d_ad[2] lcl_d_ad[1] lcl_d_ad[1] lcl_d_ad[6] lcl_d_ad[6] g40.ctl Ñ lcl_d_ad[10] lcl_d_ad[10]...
  • Page 417 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin i.obs o.pin i.obs MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Pin/Cell Name Pin Type g20.ctl lcl_dp_c_be[1] lcl_dp_c_be[1] g44.ctl lcl_d_ad[15] lcl_d_ad[15] g47.ctl l_a30_lock_b l_a30_lock_b g36.ctl l_a21_perr_b l_a21_perr_b g27.ctl...
  • Page 418 IO.ctl i.obs o.pin i.obs o.pin i.obs o.pin i.obs o.pin i.obs o.pin IO.ctl i.obs 12-26 MPC8260 PowerQUICC II UserÕs Manual Pin/Cell Name Pin Type lcl_d_ad[18] lcl_d_ad[19] lcl_d_ad[19] g42.ctl Ñ lcl_d_ad[20] lcl_d_ad[20] lcl_d_ad[21] lcl_d_ad[21] lcl_d_ad[22] lcl_d_ad[22] lcl_d_ad[23] lcl_d_ad[23] l_a20_idsel_b l_a20_idsel_b g26.ctl...
  • Page 419 IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs o.pin IO.ctl i.obs MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port Part III. The Hardware Interface Pin/Cell Name Pin Type l_a25_gnt0_b g31.ctl Ñ l_a27_pclk l_a27_pclk g33.ctl Ñ l_a28_rst_b l_a28_rst_b g34.ctl...

  • Page 420: Instruction Register

    (HI-Z) can be used to disable all device output drivers. The MPC8260 includes a 4-bit instruction register (no parity) that consists of a shift register with four parallel outputs. Data is transferred from the shift register to the parallel outputs during the update-IR controller state.
  • Page 421 Þnally, to TDO, circumventing the 475-bit boundary scan register. This instruction is used to enhance test efÞciency when a component other than the MPC8260 becomes the device under test. It selects the single- bit bypass register as shown below. Shift DR...

  • Page 422: Mpc8260 Restrictions

    The control afforded by the output enable signals using the boundary-scan register and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive conÞgurations. The user must avoid situations in which the MPC8260Õs output drivers are enabled into actively driven networks.
  • Page 423 Intended Audience Part IV is intended for system designers who need to implement various communications protocols on the MPC8260. It assumes a basic understanding of the PowerPC exception model, the MPC8260 interrupt structure, as well as a working knowledge of the communications protocols to be used.
  • Page 424 WANs, LANs, and proprietary networks. ¥ Chapter 20, ÒSCC UART Mode,Ó describes the MPC8260 implementation of universal asynchronous receiver transmitter (UART) protocol that is used for sending low-speed data between devices.
  • Page 425 MC68360, the MC68302, the M68HC11, and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. ¥ Chapter 34, ÒI2C Controller,Ó describes the MPC8260 implementation of the inter- integrated circuit (I C¨) controller, which allows data to be exchanged with other C devices, such as microcontrollers, EEPROMs, real-time clock devices, and A/D converters.
  • Page 426 Part IV. Communications Processor Module ¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide (Motorola order #: MPCPRG/D) is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set. For a current list of PowerPC documentation, refer to the world-wide web at http://www.mot.com/PowerPC.
  • Page 427 Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory Free buffer pool FIFO First-in-Þrst-out (buffer) General circuit interface GCRA Generic cell rate algorithm (leaky bucket) GPCM General-purpose chip-select machine MOTOROLA Part IV. Communications Processor Module Part IV. Communications Processor Module Meaning Part IV-v...
  • Page 428 Machine state register Not a number Network interface card Network interface unit NMSI Nonmultiplexed serial interface Non-real time Open systems interconnection Peripheral component interconnect Protocol data unit Peak cell rate Physical layer Pulse-position modulation Resource management Part IV-vi Meaning MOTOROLA...
  • Page 429 Transmit UnspeciÞed bit rate UBR+ UnspeciÞed bit rate with minimum cell rate guarantee UART Universal asynchronous receiver/transmitter User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter Wide area network MOTOROLA Part IV. Communications Processor Module Part IV. Communications Processor Module Meaning Part IV-vii...
  • Page 430 Part IV. Communications Processor Module Part IV-viii MOTOROLA...

  • Page 431: Communications Processor Module Overview

    Communications Processor Module Overview The MPC8260Õs communications processor module (CPM) is a superset of the MPC860 PowerQUICC CPM, with enhancements in performance and the addition of hardware and microcode routines for supporting high bit-rate protocols like ATM and Fast Ethernet. The support for multiple HDLC channels is enhanced to support up to 256 HDLC channels.
  • Page 432 ¥ Eight independent baud rate generators (BRGs) ¥ Four general-purpose 16-bit timers or two 32-bit timers ¥ General-purpose parallel portsÑsixteen parallel I/O lines with interrupt capability Figure 13-1 shows the MPC8260Õs CPM block diagram. 13-2 MPC8260 PowerQUICC II UserÕs Manual...
  • Page 433 3 FCCs Figure 13-1. MPC8260 CPM Block Diagram 13.2 MPC8260 Serial ConÞgurations The MPC8260 offers a ßexible set of communications capabilities. A subset of the possible conÞgurations using an MPC8260 is shown in Table 13-1. Table 13-1. Possible MPC8260 Applications...

  • Page 434: Communications Processor (Cp)

    ¥ Special registers, CRC machine, HDLC framer The CP also gives SDMA commands to the SDMA. The CP interfaces with the dual-port RAM for loading and storing data and for fetching instructions while running microcode from dual-port RAM. 13-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 435 Figure 13-2 shows the CP block diagram. Data Data Scheduler Sequencer Microcode Figure 13-2. Communications Processor (CP) Block Diagram MOTOROLA Chapter 13. Communications Processor Module Overview Part IV. Communications Processor Module Communications Processor (CP) Timer Special Execution Registers Unit Source Buses...

  • Page 436: Powerpc Core Interface

    FCC1 receive FCC1 transmit MCC1 receive MCC2 receive MCC1 transmit MCC2 transmit FCC2 receive FCC2 transmit FCC3 receive FCC3 transmit SCC1 receive SCC1 transmit SCC2 receive 13-6 MPC8260 PowerQUICC II UserÕs Manual C are all double-buffered, creating effective Request MOTOROLA...

  • Page 437: Execution From Ram

    ROM. This mode allows Motorola to add new protocols or enhancements to the MPC8260 in the form of RAM microcode packages. If preferred, the user can obtain binary microcode from Motorola and load it into the dual-port RAM.

  • Page 438: Risc Controller Configuration Register (Rccr)

    11 Reserved External interrupt enable. When EIE is set, DREQ1 acts as an external interrupt to the CP. ConÞgure as instructed in the download process of a Motorola-supplied RAM microcode package. 0 DREQ1 cannot interrupt the CP. 1 DREQ1 will interrupt the CP.

  • Page 439: Risc Time-Stamp Control Register (Rtscr)

    Bits Name 16Ð18 ERAM Enable RAM microcode. ConÞgure as instructed in the download process of a Motorola-supplied RAM microcode package. 000 Disable microcode program execution from the dual-port RAM. 001 Microcode uses the Þrst 2 Kbytes of the dual-port RAM.

  • Page 440: Risc Time-Stamp Register (Rtsr)

    REV_NUM that resides in the miscellaneous parameter RAM. The other locations are reserved for future use. Table 13-5. RISC Microcode Revision Number Address Name RAM Base + 0x8AF0 REV_NUM RAM Base + 0x8AF2 Ñ 13-10 MPC8260 PowerQUICC II UserÕs Manual Description Time Stamp Ñ 0x119E0 Time Stamp Ñ 0X119E2 Width Hword...

  • Page 441: Command Set

    1Ð5 PAGE Indicates the parameter RAM page number associated with the sub-block being served. See the SBC description for page numbers. MOTOROLA Chapter 13. Communications Processor Module Overview Part IV. Communications Processor Module command must be issued through the CP...
  • Page 442 0x00 HDLC 0x0A ATM 0x0C Ethernet 0x0F Transparent 26-27 Ñ Reserved 28Ð31 OPCODE Operation code. Settings are listed in Table 13-7 below. 13-12 MPC8260 PowerQUICC II UserÕs Manual Code Page Sub-block 10000 00100 (for ATM: 01110) 10001 00101 (for ATM: 01110)

  • Page 443: Cp Commands

    RESET BCS TRANSMIT COMMAND 1011 Ñ Ñ 1100 Ñ Ñ UndeÞned. Reserved for use by Motorola-supplied RAM microcodes. MOTOROLA Chapter 13. Communications Processor Module Overview Part IV. Communications Processor Module Channel (UART/ (GCI) INIT RX AND INIT RX INIT RX...
  • Page 444 MCC STOP RECEIVE See Section 29.14, ÒATM Transmit Command.Ó ATM TRANSMIT Generate a random number and put it in dual-port RAM; see RAND in Table 13-10. RANDOM NUMBER 13-14 MPC8260 PowerQUICC II UserÕs Manual Description command is issued. RESTART MOTOROLA...

  • Page 445: Command Register Example

    ¥ CP instruction fetcher (when executing microcode from RAM) ¥ PowerPCª 60x slave ¥ SDMA 60x bus ¥ SDMA local bus Figure 13-8 shows the memory map of the dual-port RAM. MOTOROLA Chapter 13. Communications Processor Module Overview Part IV. Communications Processor Module Slave Data Dual-Port RAM...
  • Page 446 ¥ For temporary storage of FCC data moving to/from an FCC FIFO (using the BTM) from/to external memory (using SDMA). ¥ To store RAM microcode for the CP. This feature allows Motorola to add protocols in the future. ¥ For additional scratch-pad RAM space for user software.

  • Page 447: Buffer Descriptors (Bds)

    The exact deÞnition of the parameter RAM is contained in each protocol subsection describing a device that uses a parameter RAM. For example, the Ethernet parameter RAM is deÞned differently in some locations from the HDLC-speciÞc parameter RAM. MOTOROLA Chapter 13. Communications Processor Module Overview Part IV. Communications Processor Module...

  • Page 448: Risc Timer Tables

    BRGs in the CPM. These timers are best used in protocols that do not require extreme precision, but in which it is preferable to free the core from scanning the softwareÕs 13-18 MPC8260 PowerQUICC II UserÕs Manual Table 13-10. Parameter RAM Address...

  • Page 449: Risc Timer Table Parameter Ram

    Two areas of dual-port RAM, shown in Figure 13-9, are used for the RISC timer tables: ¥ The RISC timer table parameter RAM ¥ The RISC timer table entries 0x8AE0 Figure 13-9. RISC Timer Table RAM Usage MOTOROLA Chapter 13. Communications Processor Module Overview Part IV. Communications Processor Module 16 RISC Timer Table...

  • Page 450: Risc Timer Command Register (Tm_Cmd)

    Figure 13-10 shows the RISC timer command register (TM_CMD). Bits Field Bits Field Figure 13-10. RISC Timer Command Register (TM_CMD) 13-20 MPC8260 PowerQUICC II UserÕs Manual Description command should be used instead. Ñ TIMER PERIOD (TP) command is SET TIMER command.

  • Page 451: Risc Timer Table Entries

    Field TMR1 TMR1 TMR1 TMR1 Addr Figure 13-12. RISC Timer Event Register (RTER)/Mask Register (RTMR) MOTOROLA Chapter 13. Communications Processor Module Overview Part IV. Communications Processor Module Description command and the next half-word is the current value of the TMR1...

  • Page 452: Set Timer Command

    2. ConÞgure the TM_BASE in the RISC timer table parameter RAM to point to a location in the dual-port RAM with 4 bytes available. Assuming the beginning of dual-port RAM is available, write 0x0000 to TM_BASE. 13-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 453: Risc Timer Interrupt Handling

    RAM, but does not scan the timer table until the next tick of the internal timer. It is important to use the modiÞcations to the execution of the CP. MOTOROLA Chapter 13. Communications Processor Module Overview Part IV. Communications Processor Module SET TIMER commands at this time or later, as preferred.

  • Page 454: Using The Risc Timers To Track Cp Loading

    CP has, during some tick interval, exceeded the 96% utilization level. General-purpose timers are up counters, but RISC timers are down counters. The user should take this under consideration when comparing timer counts. 13-24 MPC8260 PowerQUICC II UserÕs Manual NOTE: MOTOROLA...

  • Page 455: Serial Interface With Time-Slot Assigner

    Chapter 14 Serial Interface with Time-Slot Assigner Figure 14-1 shows a block diagram of the TSA. Two SI blocks in the MPC8260 (SI1 and SI2), can be programmed to handle eight TDM lines concurrently with the same ßexibility described in this manual. TDM channels on SI1 are referred to as TDMa1, TDMb1, TDMc1, TDMd1;...
  • Page 456 If the time-slot assigner (TSA) is not used as intended, it can be used to generate complex wave forms on dedicated output pins. For instance, it can program these pins to implement stepper motor control or variable-duty cycle and period control on-the-ßy. 14-2 MPC8260 PowerQUICC II UserÕs Manual Tx/Rx Mode Command...

  • Page 457: Features

    128 channels (all four channels can support up to 128 channels together). ¥ Independent mapping for receive/transmit ¥ Individual channel echo or loop mode ¥ Global echo or loop mode through the SI MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module 14-3...

  • Page 458: Overview

    8 bits or even to a single contiguous position within the frame. Finally, the user can provide separate receive and transmit syncs as well as clocks. Figure 14-2 shows example TSA conÞgurations ranging from the simplest to the most complex. 14-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 459 MPC8260 1 TDM Sync 1 TDM Clock MPC8260 1 TDM Sync 1 TDM Clock Even more complex TDM exampleÑmultiple time slot per channel with varying sizes of time slots MPC8260 1 TDM Sync 1 TDM Clock NOTE: The two shaded areas off SCC2 Rx are received as one high-speed data stream by SCC2 Rx stored together in the same data buffers Most complex TDM example ÑTotally independent Rx and Tx...
  • Page 460 Most TSA programming is done in the two 256- ´ 16-bit SIx RAMs. These SIx RAMs are directly accessible by the core in the internal register section of the MPC8260 and are not 14-6 MPC8260 PowerQUICC II UserÕs Manual...

  • Page 461: Enabling Connections To Tsa

    TSA and the serial interfaces. The connection is made by programming the CPM mux. See Chapter 15, ÒCPM Multiplexing.Ó Once the connections are made, the exact routing decisions are made in the SIx RAM. MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module...

  • Page 462: Serial Interface Ram

    RAM has a shadow for changing SIx RAM entries while the TDM channel is active. This reduces the number of available SIx RAM entries for that TDM. 14-8 MPC8260 PowerQUICC II UserÕs Manual TDM a,b,c,d Enable = 1 TDM a Pins...

  • Page 463: One Multiplexed Channel With Static Frames

    After programming the shadow RAM, the user sets SIxCMDR[CSRxn] for the associated channel. When the next frame sync arrives, the SI automatically exchanges the current- route RAM for the shadow RAM. See Section 14.4.5, ÒStatic and Dynamic Routing.Ó MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module...

  • Page 464: Programming Six Ram Entries

    MCC = 1 LOOP/ECHO SUPER Addr Figure 14-7. SI x RAM Entry Fields When MCC = 0, the SI x RAM entry Þelds function as described in Table 14-1. 14-10 MPC8260 PowerQUICC II UserÕs Manual Framing Signals L1TCLKa x 128 Entries L1TSYNCa x...
  • Page 465 0101 The bit/byte group is routed to SMC1. 0110 The bit/byte group is routed to SMC2. 0111 The bit/byte group is not supported by the MPC8260. This code is also used in SCIT mode as the D channel grant. See Section 14.7.2.2, ÒSCIT Programming.Ó...
  • Page 466 Note that if the transmit and receive sections of the TDM do not use a common clock source, the SWTR feature can cause erratic behavior. Note also this feature does not work with nibble operation. 14-12 MPC8260 PowerQUICC II UserÕs Manual Description L1RXD L1TXD...

  • Page 467: Six Ram Programming Example

    (using a strobe to enable the external device), and the last 4 bits of B2 with SMC1. Additionally, the TSA marks the D channel with another strobe signal. MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module...

  • Page 468: Static And Dynamic Routing

    Ñ All serial devices connected to the TSA must be disabled. Ñ SI routing can be modiÞed. Ñ All appropriate serial devices connected to the TSA must be reenabled. 14-14 MPC8260 PowerQUICC II UserÕs Manual SI x RAM Entry SSEL CSEL...
  • Page 469 SI x RAM entry starting or ending execution by the TSA. An example is shown in Figure 14-9. MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module...
  • Page 470 RAM Address: CSRTa=0 CSRRb=0 CSRTb=0 Framing Signals: Figure 14-9. Example: SI x RAM Dynamic Changes, TDMa and b, Same SI x RAM Size 14-16 MPC8260 PowerQUICC II UserÕs Manual 127 128 255 256 64 TXb 64 TXa 64 TXa Route...

  • Page 471: Serial Interface Registers

    (with SIx RAM) to support any or all of the ISDN channels independently when in IDL or GCI mode. Any extra serial channel can then be used for other purposes. MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module...
  • Page 472 This mode is used to accomplish loopback testing of the entire TDM without affecting the external serial lines. Note: In modes 01, 10, and 11, the receive and transmit clocks should be identical. 14-18 MPC8260 PowerQUICC II UserÕs Manual SDMx RFSDx DSCx...
  • Page 473 See Figure 14-13, Figure 14-14, Figure 14-15, and Figure 14-16. 0 Falling edge. Use for IDL and GCI. 1 Rising edge. MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module Description...
  • Page 474 L1SYNC (FE=1) Data Bit-0 No Delay from Sync Latch to First Bit of Frame Figure 14-13. No Delay from Sync to Data (xFSD = 00) 14-20 MPC8260 PowerQUICC II UserÕs Manual Description End of Frame Bit-1 Bit-2 Bit-3 Bit-4 Bit-5...
  • Page 475 L1SYNC L1TXD (Bit-0) L1ST (On Bit-0) Figure 14-15. Falling Edge (FE) Effect When CE = 0 and xFSD = 01 MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module xFSD=01 (FE=0) (FE=1) L1ST Driven from Clock High for Both FE Settings...
  • Page 476 L1ST (On Bit-0) Figure 14-16. Falling Edge (FE) Effect When CE = 1 and xFSD = 00 14-22 MPC8260 PowerQUICC II UserÕs Manual The L1ST is Driven from Sync. Data is Driven from Clock Low. Rx Sampled Here L1ST is Driven from Clock High.

  • Page 477: Six Ram Shadow Address Registers (Sixrsr)

    The SIx RAM shadow address registers (SIxRSR), shown in Figure 14-18, deÞne the starting addresses of the shadow section in the SIx RAM for each of the TDM channels. MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module The L1ST is Driven from Sync.

  • Page 478: Si Command Register (Sixcmdr)

    For more information about dynamic programming, see Section 14.4.5, ÒStatic and Dynamic Routing.Ó Bits Field CSRRA CSRTA Reset Addr Figure 14-19. SI Command Register (SIxCMDR) 14-24 MPC8260 PowerQUICC II UserÕs Manual Ñ SSADB Ñ 0000_0000_0000_0000 0x11B2E (SI1RSR), 0x11B4E (SI2RSR) Description CSRRB CSRTB CSRRC...

  • Page 479: Si Status Registers (Sixstr)

    14.6 Serial Interface IDL Interface Support The IDL interface is a full-duplex ISDN interface used to connect a physical layer device to the MPC8260. The MPC8260 supports both the basic and primary rate of the IDL bus. MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV.

  • Page 480: Idl Interface Example

    MPC8260, CODEC, and S/T transceiver. One of the MPC8260Õs SCCs is conÞgured to HDLC mode to handle the D channel; another MPC8260Õs SCC is used to rate adapt the terminal data stream over the Þrst B channel. That SCC is conÞgured for HDLC mode if V.120 rate adoption is required.
  • Page 481 L1RSYNCx IDL sync signal; input to the MPC8260. This signal indicates that the clock periods following the pulse designate the IDL frame. L1RXDx IDL receive data; input to the MPC8260. Valid only for the bits supported by the IDL; ignored for any other signals present. L1TXDx IDL transmit data;...
  • Page 482 The MPC8260 supports the request-grant method for contention detection on the D channel of the IDL basic rate and when the MPC8260 has data to transmit on the D channel, it asserts L1RQx. The physical layer device monitors the physical layer bus for activity on the D channel and indicates that the channel is free by asserting L1GRx.

  • Page 483: Idl Interface Programming

    This procedure is handled automatically for the Þrst two buffers of a frame. For the primary rate IDL, the MPC8260 supports up to four 8-bit channels in the frame, determined by the SIx RAM programming. To support more channels, the user can route more than one channel to each SCC and the SCC treats it as one high-speed stream and store it in the same data buffers (appropriate only for transparent data).
  • Page 484 13. Set PPARB[17]. ConÞgures L1RQa. 14. Clear PSORB[17]. ConÞgures L1RQa. 15. Set PDIRB[17]. ConÞgures L1RQa. 16. Set PPARD[13]. ConÞgures L1ST1. 17. Clear PSORD[13]. ConÞgures L1ST1. 18. Set PDIRD[13]. ConÞgures L1ST1. 14-30 MPC8260 PowerQUICC II UserÕs Manual SIx RAM Entry SSEL CSEL 0000 0010 0000...

  • Page 485: Serial Interface Gci Support

    Used as a GCI sync signal; input to the MPC8260. This signal indicates that the clock periods following the pulse designate the GCI frame. L1RCLKx Used as a GCI clock; input to the MPC8260. The L1RCLKx signal frequency is twice the data clock. L1RXDx Used as a GCI receive data; input to the MPC8260.
  • Page 486 The MPC8260 supports contention detection on the D channel of the SCIT bus. When the MPC8260 has data to transmit on the D channel, it checks a SCIT bus bit that is marked with a special route code (usually, bit 4 of C/I channel 2). The physical layer device monitors the physical layer bus for activity on the D channel and indicates on this bit that the channel is free.

  • Page 487: Si Gci Activation/Deactivation Procedure

    In the deactivated state, the clock pulse is disabled and the data line is at a logic one. The layer 1 device activates the MPC8260 by enabling the clock pulses and by an indication in the channel 0 C/I channel. The MPC8260 reports to the core (via a maskable interrupt) that a valid indication is in the SMC RxBD.
  • Page 488 10. Set PPARC[30,31]. ConÞgures L1TCLKa and L1RCLKa. 11. Clear PDIRC[30,31]. ConÞgures L1TCLKa and L1RCLKa. 12. Clear PSORC[30,31]. ConÞgures L1TCLKa and L1RCLKa. 13. Set PPARB[17]. ConÞgures L1CLKO and L1RQa. 14-34 MPC8260 PowerQUICC II UserÕs Manual SIx RAM Entry SSEL CSEL 0000...
  • Page 489 18. SI1GMR = 0x11. Enable TDMa (one static TDM), STZ for TDMa. 19. SI1CMDR is not used. 20. SI1STR does not need to be read. 21. Enable the SCC1, SCC2, SMC1 and SMC2. MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner Part IV. Communications Processor Module 14-35...
  • Page 490 Part IV. Communications Processor Module 14-36 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 491: Cpm Multiplexing

    CMX to connect a serial device to the SI, the CMX connects that serial device to both SIs. Programming both SIs to use one serial device in the same time slot causes erratic behavior. Figure 15-1 shows a block diagram of the CMX. MOTOROLA NOTE Chapter 15. CPM Multiplexing 15-1...

  • Page 492: Features

    ¥ Each SMC can have its own set of four pins. ¥ Each FCC, SCC, and SMC can be driven from a bank of twenty clock pins or a bank of eight BRGs. 15-2 MPC8260 PowerQUICC II UserÕs Manual Register Bus UTOPIA Address...

  • Page 493: Enabling Connections To Tsa Or Nmsi

    SMC can be connected to the eight TDMs or to its own set of pins. Once connections are made to the TSA, the exact routing decisions are made in the SIx RAMs. MOTOROLA Part IV. Communications Processor Module Chapter 15. CPM Multiplexing...
  • Page 494 The user should note, however, that NMSI pins are multiplexed with other functions at the parallel I/O lines. Therefore, if a combination of TDM and NMSI channels are used, consult the MPC8260Õs pinout to determine which FCC, SCC, and SMC to connect and where to connect them.
  • Page 495 ¥ The SMC transmitter and receiver share the same clock source when connected to the NMSI. Table 15-1 shows the clock source options for the serial controllers and TDM channels. MOTOROLA Part IV. Communications Processor Module BRG5 BRG6...

  • Page 496: Cmx Registers

    SCCs, the names are RCLKx and TCLKx; for SMCs, the name is simply SMCLKx. These internal names are used only in NMSI mode to specify the clocks sent to the FCCs, SCCs or SMCs. These names do not correspond to any MPC8260 pins. 15.4 CMX Registers The following sections describe the CMX registers.

  • Page 497: Cmx Utopia Address Register (Cmxuar)

    FCC1 and FCC2 UTOPIA multiple-PHY addresses to the twenty UTOPIA address pins of the MPC8260; it also deÞnes the connection of a BRG to the FCCs when an internal rate feature is used. This enables the user to implement a multiple-PHY UTOPIA master or slave on both FCC1 and FCC2 using only twenty pins.
  • Page 498 Note that each SADx and MADx corresponds to a pair of separate receive and transmit address pins. The MPC8260 has 16 output address pins and 10 input address pins dedicated for the UTOPIA interface. However, it has two FCCs with two parts eachÑreceiver and transmitter that can be ether master or slave concurrently.
  • Page 499 Figure 15-7 describes the interconnection between the receive external multi-PHY bus and the internal FCC1 and FCC2 receive multi-PHY addresses. The same diagram applies to the transmit multi-PHY bus using different dedicated parallel I/O pins. MOTOROLA Part IV. Communications Processor Module Chapter 15. CPM Multiplexing...

  • Page 500: Cmx Si1 Clock Route Register (Cmxsi1Cr)

    15.4.2 CMX SI1 Clock Route Register (CMXSI1CR) The CMX SI1 clock route register (CMXSI1CR) deÞnes the connection of SI1 to the clock sources that can be input from the bank of clocks. 15-10 MPC8260 PowerQUICC II UserÕs Manual MAD4 MAD3 SAD4...

  • Page 501: Cmx Si2 Clock Route Register (Cmxsi2Cr)

    15.4.3 CMX SI2 Clock Route Register (CMXSI2CR) The CMX SI2 clock route register (CMXSI2CR) deÞnes the connection of SI2 to the clock sources that can be input from the bank of clocks. MOTOROLA Part IV. Communications Processor Module RTC1CS RTD1CS...

  • Page 502: Cmx Fcc Clock Route Register (Cmxfcr)

    15.4.4 CMX FCC Clock Route Register (CMXFCR) The CMX FCC clock route register (CMXFCR) deÞnes the connection of the FCCs to the TSA and to the clock sources from the bank of clocks. 15-12 MPC8260 PowerQUICC II UserÕs Manual RTC2CS RTD2CS TTA2CS...
  • Page 503 The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O control register. 1 FCC2 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes. MOTOROLA Part IV. Communications Processor Module TF1CS Ñ...

  • Page 504: Cmx Scc Clock Route Register (Cmxscr)

    The CMX SCC clock route register (CMXSCR) deÞnes the connection of the SCCs to the TSA and to the clock sources from the bank of clocks. This register also enables the use of the external grant pin. 15-14 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...
  • Page 505 011 SCC1 transmit clock is BRG4. 100 SCC1 transmit clock is CLK11. 101 SCC1 transmit clock is CLK12. 110 SCC1 transmit clock is CLK3. 111 SCC1 transmit clock is CLK4. MOTOROLA Part IV. Communications Processor Module TS1CS GR2 SC2 0000_0000_0000_0000...
  • Page 506 010 SCC3 receive clock is BRG3. 011 SCC3 receive clock is BRG4. 100 SCC3 receive clock is CLK5. 101 SCC3 receive clock is CLK6. 110 SCC3 receive clock is CLK7. 111 SCC3 receive clock is CLK8. 15-16 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 507: Cmx Smc Clock Route Register (Cmxsmr)

    15.4.6 CMX SMC Clock Route Register (CMXSMR) The CMX SMC clock route register (CMXSMR) deÞnes the connection of the SMCs to the TSA and to the clock sources from the bank of clocks. MOTOROLA Part IV. Communications Processor Module Description Chapter 15.
  • Page 508 00 SMC2 transmit and receive clocks are BRG2. 01 SMC2 transmit and receive clocks are BRG8. 10 SMC2 transmit and receive clocks are CLK19. 11 SMC2 transmit and receive clocks are CLK20. 15-18 MPC8260 PowerQUICC II UserÕs Manual SMC1CS SMC2 0000_0000 0x11B0C Description Ñ...

  • Page 509: Baud-Rate Generators (Brgs)

    EXTC CLK Pin x Clock CLK Pin y Source BRGCLK Autobaud RXDn Control Figure 16-1. Baud-Rate Generator (BRG) Block Diagram MOTOROLA Chapter 16. Baud-Rate Generators (BRGs) DIV 16 CD[0Ð11] Prescaler Divide by 12-Bit Counter 1 or 16 1Ð4,096 BRGOn Clock...
  • Page 510 Part IV. Communications Processor Module Each BRG clock source can be BRGCLK, or a choice of two external clocks (selected in BRGCx[EXTC]). The BRGCLK is an internal signal generated in the MPC8260 clock synthesizer speciÞcally for the BRGs, the SPI, and the I external clock pins can be conÞgured as clock sources.
  • Page 511 DIV16 Divide-by-16. Selects a divide-by-1 or divide-by-16 prescaler before reaching the clock divider. See Section 16.3, ÒUART Baud Rate Examples.Ó 0 Divide by 1. 1 Divide by 16. Table 16-2 shows the possible external clock sources for the BRGs. MOTOROLA Chapter 16. Baud-Rate Generators (BRGs) Part IV. Communications Processor Module Description 16-3...

  • Page 512: Autobaud Operation On A Uart

    BRGCx[ATB] and enable the BRG Rx clock to the highest frequency. Then, immediately before the autobaud process starts (after device initialization), set BRGCx[ATB]. 16-4 MPC8260 PowerQUICC II UserÕs Manual 9 10 11 12 13 14 15 16 17 18 19 20 MOTOROLA...

  • Page 513: Uart Baud Rate Examples

    BRGCx[DIV16] 1200 2400 4800 9600 19,200 38,400 57,600 115,200 460,000 MOTOROLA Chapter 16. Baud-Rate Generators (BRGs) Part IV. Communications Processor Module BRGCLK or External Clock Source · Clock Divider + 1 BRGCx[EXTC] · BRGCx[CD] + 1 Using 66-MHz System Clock...
  • Page 514 Sync Baud Rate For example, to get a rate of 64 kbps, the system clock can be 24.96 MHz, BRGCx[DIV16] = 0, and BRGCx[CD] = 389. 16-6 MPC8260 PowerQUICC II UserÕs Manual BRGCLK or External Clock Source -------------------------------------------------------------------------------------------------- · Prescale Divider...
  • Page 515 Reference Register TCR1 Capture Register Timer1 Timer2 Timer3 Timer4 Figure 17-1. Timer Block Diagram Pin assignments for TINx, TGATEx, and TOUTx are described in Section 35.5, ÒPorts Tables.Ó MOTOROLA General System Clock Timer Clock Generator Mode Bits Clock Capture Detection Chapter 17.

  • Page 516: Features

    TMR[ORI] = 1. The timers can output a signal on the timer outputs (TOUT1ÐTOUT4) when the reference value is reached (selected by the corresponding TMR[OM]). This signal can be an active-low pulse or a toggle of the current output. The 17-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 517: Cascaded Mode

    Because the decision to cascade timers is made independently, the user can select two 16- bit timers or one 32-bit timer. TGCR is used to put the timers into cascaded mode, as shown in Figure 17-2. MOTOROLA Part IV. Communications Processor Module NOTE Chapter 17.
  • Page 518 The clocks to the timer remain stopped until the user clears this bit or a hardware reset occurs. 17-4 MPC8260 PowerQUICC II UserÕs Manual TRR, TCR, TCN connected to D[16Ð31] Capture TRR, TCR, TCN connected to D[16Ð31]...
  • Page 519 RST4 Reset timer. 0 Reset the corresponding timer (a software reset is identical to an external reset). 1 Enable the corresponding timer if the STP bit is cleared. MOTOROLA Part IV. Communications Processor Module Description STP4 RST4...

  • Page 520: Timer Mode Registers (Tmr1Ðtmr4)

    01 Capture on rising TINx edge only and enable interrupt on capture event. 10 Capture on falling TINx edge only and enable interrupt on capture event. 11 Capture on any TINx edge and enable interrupt on capture event. 17-6 MPC8260 PowerQUICC II UserÕs Manual Description 0000_0000_0000_0000 Description...

  • Page 521: Timer Reference Registers (Trr1Ðtrr4)

    The reference value is not reached until TCNx increments to equal the timeout reference value. Field Reset Addr 0x10D94 (TRR1), 0x10D96 (TRR2), 0x10DA4 (TRR3), 0x10DA6 (TRR4) Figure 17-6. Timer Reference Registers (TRR1ÐTRR4) MOTOROLA Part IV. Communications Processor Module Description Timeout reference value 0xFFFF Chapter 17. Timers 17-7...

  • Page 522: Timer Capture Registers (Tcr1Ðtcr4)

    Bits Field Reset Addr 0x10DB0 (TER1); 0x10DB2 (TER2); 0x10DB4 (TER3); 0x10DB6 (TER4) Figure 17-9. Timer Event Registers (TER1ÐTER4) 17-8 MPC8260 PowerQUICC II UserÕs Manual Latched counter value 0x0000 Up counter 0x0000 Ñ 0x0000 REF CAP...
  • Page 523 Output reference event. The counter has reached the TRR value. TMR[ORI] is used to enable the interrupt request caused by this event. Capture event. The counter value has been latched into the TCR. TMR[CE] is used to enable generation of this event. MOTOROLA Part IV. Communications Processor Module Description Chapter 17. Timers...
  • Page 524 Part IV. Communications Processor Module 17-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 525: Sdma Channels And Idma Emulation

    Chapter 18 SDMA Channels and IDMA Emulation The MPC8260 has two physical serial DMA (SDMA) channels. The CP implements two dedicated virtual SDMA channels for each FCC, MCC, SCC, SMC, SPI, and I each transmitter and receiver. An additional four virtual SDMA channels are assigned to the programmable independent DMA (IDMA) channels.

  • Page 526: Sdma Bus Arbitration And Bus Transfers

    ÒSDMA Registers.Ó 18.1 SDMA Bus Arbitration and Bus Transfers On the MPC8260, the core and SDMA can become external bus masters. (The relative priority of these masters is programmed by the user; see Section 4.3.2, ÒSystem ConÞguration and Protection RegistersÓ for programming bus arbitration.) Therefore, any SDMA channel can arbitrate for the bus against the other internal devices and any external devices present.

  • Page 527: Sdma Registers

    This bit is cleared writing a 1; writing a zero has no effect. The SDMA transfer error address can be read from LDTEA, and the channel number from LDTEM. 2Ð7 Ñ Reserved, should be cleared. MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation Part IV. Communications Processor Module SDMA Transaction Ñ...

  • Page 528: Sdma Mask Register (Sdmr)

    Bit 5 of MSNUM indicates which section of the peripheral controller is accessing the bus. 0 Transmit section 1 Receive section 6Ð7 Ñ Reserved, should be cleared. 18-4 MPC8260 PowerQUICC II UserÕs Manual MSNUM Ñ 0x10054 (PDTEM); 0x1005C (LDTEM) Description Ñ MOTOROLA...

  • Page 529: Idma Emulation

    The chip-select and wait-state generation logic on the MPC8260 can be used with the IDMA. The bus bandwidth occupied by the IDMA can be programmed in the IDMA parameter RAM to achieve maximum system performance.

  • Page 530: Idma Transfers

    When alignment is achieved, subsequent data is bursted until the remainder of the data in the buffer is less than a burst size (32 bytes). The remaining data is transferred using non- burst transactions. Data transfers use the parameters described in Table 18-3. 18-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 531 Þrst phase, all bus transfers are bursts. This sequence is repeated until there are no more than SS_MAX bytes to be transferred. A remainder of 0Ð31 bytes is left in the transfer buffer after the last burst write. MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation Part IV. Communications Processor Module...

  • Page 532: External Request Mode

    DREQ. When the transfer buffer is full, the Þrst write transfer is done automatically. Additional write transfers, if needed, are triggered by DREQ assertions. 18-8 MPC8260 PowerQUICC II UserÕs Manual EOB (destination) Read size = EOB(source) + SS_MAX...

  • Page 533: Normal Mode

    Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó This allows the IDMA to access a FIFO buffer the same way it does peripherals. DCM[S/D] determines whether the peripheral is the source or destination. MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation Part IV. Communications Processor Module...

  • Page 534: Dual-Address Transfers

    The Þrst DREQ peripheral assertion triggers a read of SS_MAX (or more in the Þrst phase) bytes from the memory into the internal transfer buffer, automatically followed by a write of DTS bytes to the peripheral. Subsequent DREQ assertions trigger writes to the 18-10 MPC8260 PowerQUICC II UserÕs Manual STOP IDMA MOTOROLA...

  • Page 535: Single Address (Fly-By) Transfers

    Thus, data is transferred from memory to a peripheral in one data phase instead of two, increasing throughput. For proper operation, DTS must equal the peripheral port size. MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-11...

  • Page 536: Controlling 60X Bus Bandwidth

    Additional priority over all serial controllers can be selected by setting DCM[LP]; see Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó 18.7 IDMA Interface Signals Each IDMA has three dedicated handshake control signals for transfers involving an external peripheral device: DMA request (DREQ[1Ð4]), DMA acknowledge (DACK[1Ð4]) 18-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 537: Dreqx And Dackx

    See Chapter 35, ÒParallel I/O Ports.Ó 18.7.1 DREQx and DACKx When the peripheral requires IDMA service, it asserts DREQx and the MPC8260 begins the IDMA process. When the IDMA service is in progress, DACKx is asserted during accesses to the peripheral.

  • Page 538: Donex

    The IDMA can interrupt the core if interrupts are enabled to signal for operation termination and other events related to the data transfer. The IDMA uses a data structure, which, as with serial controller BDs, allows ßexible data 18-14 MPC8260 PowerQUICC II UserÕs Manual NOTE command. START...

  • Page 539: Auto Buffer And Buffer Chaining

    BD and so forth. The Þrst BD is reused (if ready) until the BD with the last bit set is reached. IDMA transfers stop and restarts when the BD table is reinitialized and a START MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation Part IV. Communications Processor Module BD 0...

  • Page 540: Idmax Parameter Ram

    18.8.2 IDMAx Parameter RAM When an IDMAx channel is conÞgured to auto buffer or buffer chaining mode, the MPC8260 uses the IDMAx parameters listed in the Table 18-4. Parameters should be modiÞed only while the channel is disabled, that is, before the Þrst or when the event registerÕs stop-completed bit (IDSR[SC]) is set following a...
  • Page 541 Word From the pointer value programmed in IDMAx_BASE: IDMA1_BASE at 0x87FE, IDMA2_BASE at 0x88FE, IDMA3_BASE at 0x89FE, and IDMA4_BASE at 0x8AFE; see Section 13.5.2, ÒParameter RAM.Ó MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation Part IV. Communications Processor Module Description alignment and the end) are written to the bus using this parameter.

  • Page 542: Dma Channel Mode (Dcm)

    Table 18-7 and Table 18-8 describes the relations between the parameterÕs initial value and SS_MAX, STS, DTD and DCM[S/D] parameters. The IDMA transfer buffer (DPR_BUF) size should be consistent with DCM[DMA_WRAP]; that is DPR_BUF = 64 X 2 18-18 MPC8260 PowerQUICC II UserÕs Manual Ñ DMA_WRAP Ñ Figure 18-8. DCM Parameters...
  • Page 543 It can be operated in ßy-by modeÑrespond to DACK ignoring the address. ¥ It gets highest DMA priority on the bus arbiter and the lowest DMA latency available. 18-19 MPC8260 PowerQUICC II UserÕs Manual Description command is issued. DONE assertion by a external device is ignored. IDMA...

  • Page 544: Data Transfer Types As Programmed In Dcm

    The options for setting STS and DTS depend on (DCM[DMA_WRAP]) and are described in the following tables for memory/memory and memory/peripheral transfers. 18-20 MPC8260 PowerQUICC II UserÕs Manual Description (Steady-State Operation) Read from memory: Filling internal buffer in one DMA transfer.
  • Page 545 63 * 32 Table 18-8 describes valid STS/DTS values for memory/peripheral operations. Table 18-8. Valid STS/DTS Values for Peripherals DMA_WRAP Internal Buffer Size SS_MAX MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation Part IV. Communications Processor Module STS (in Bytes)

  • Page 546: Idma Performance

    The IDMA mask register (IDMR) has the same format as IDSR. Setting IDMR bits enables, and clearing IDMR bits disables, the corresponding interrupts in the event register. Figure 18-9 shows the bit format for IDSR and IDMR. 18-22 MPC8260 PowerQUICC II UserÕs Manual S/D Mode STS (in Bytes) 15 * 32 15 * 32 1, 2, 4, 8 (single);...

  • Page 547: Idma Bds

    IDMA BDs. The CP reads the BDs, programs the SDMA channel, and notiÞes the core about the completion of a buffer transfer using the IDMA BDs. This concept is similar to the one used for the serial controllers on the MPC8260 except that the BD is larger because it contains additional information.
  • Page 548 1 The IDMA asserts DONE at the last write data phase of the BD. In ßy-by mode (DCM[FB] = 1), DDN should be same as SDN. 18-24 MPC8260 PowerQUICC II UserÕs Manual Description command is issued. After the BD is serviced this bit is...
  • Page 549 Note that if the source/destination is a device, the pointer should contain the Pointer device address. In ßy-by mode, the pointers should contain the memory address. 0x0C 0Ð31 Destination Buffer Pointer 18-25 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 550: Idma Commands

    If a is reissued, the next BD in the BD table is processed (if it is valid). 18-26 MPC8260 PowerQUICC II UserÕs Manual command can be reissued after every START...

  • Page 551: Start_Idma Command

    When a synchronous bus structure (like those supported by the MPC8260) is used, it is easy to make provisions for a bus master to detect and respond to errors during a bus transaction. The IDMA recognizes the same bus exceptions as the core, reset and transfer error, as described in Table 18-11.

  • Page 552: Programming The Parallel I/O Registers

    IDMA3 DREQ3 (I) PA[0] DACK3 (O) PA[2] DONE3 (I/O) PA[1] IDMA4 DREQ4 (I) PA[5] DACK4 (O) PA[3] DONE4 (I/O) PA[4] 18-28 MPC8260 PowerQUICC II UserÕs Manual PPARC PDIRC PODRC PPARA PDIRA PODRA PSORC Default Ñ Ñ PSORA Default Ñ Ñ...

  • Page 553: Idma Programming Examples

    Transfers to memory are 32 bytes long (60x bursts) on steady-state of work. Every BD(SDTB) = 1 Peripheral is on the 60x bus. Every BD(DDTB) = 0 Memory is on the local bus. MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation Part IV. Communications Processor Module PPARD PDIRD...

  • Page 554: Memory-To-Peripheral Fly-By Mode (Both On 60X Bus)Ñidma3

    DonÕt care. Transfer from memory to peripheral on the 60x bus is high priority. DCM[DMA_WRAP] = DC DonÕt care. No internal buffer is used. 18-30 Description command. IDMA2 page-01000 SBC-10101 op-1001 FLG=1.This write starts the START IDMA Description MPC8260 PowerQUICC II UserÕs Manual command is reissued. START IDMA MOTOROLA...
  • Page 555 BD is open with the next DREQ assertion (or IDSR[OB] interrupt is set to the core if there is no other valid BDs). 18-31 Description command. IDMA3 page-01001 SBC-10110 op-1001 FLG=1.This write starts the MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 556 Part IV. Communications Processor Module 18-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 557: Serial Communications Controllers (Sccs)

    Chapter 19 Serial Communications Controllers (SCCs) The MPC8260 has four serial communications controllers (SCCs), which can be conÞgured independently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks.

  • Page 558: Features

    DPLL can be disabled, in which case only NRZ and NRZI are supported. An SCC can be connected to its own set of pins on the MPC8260. This conÞguration is called the non-multiplexed serial interface (NMSI) and is described in Chapter 14, ÒSerial Interface with Time-Slot Assigner.Ó...

  • Page 559: The General Scc Mode Registers (Gsmr1Ðgsmr4)

    REVD TRX TTX CDP CTSP CDS CTSS Reset Addr 0x11A06 (GSMR1); 0x11A26 (GSMR2); 0x11A46 (GSMR3); 0x11A66 (GSMR4) Figure 19-2. GSMR_HÑGeneral SCC Mode Register (High Order) MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module Ñ 0000_0000_0000_0000 TFL RFW TXSY...
  • Page 560 1 CD/CTS is assumed to be synchronous with data, which speeds up operation. CD or CTS must transition while the Rx/Tx clock is low, at which time, the transfer begins. Useful for connecting MPC8260 in transparent mode since the RTS of one MPC8260 can connect directly to the CD/ CTS of another.
  • Page 561 RSYN Receive synchronization timing (totally transparent mode only). 0 Normal operation. 1 If CDS = 1 CD should be asserted on the second bit of the Rx frame rather than on the Þrst. MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module Description...
  • Page 562 1 Invert data before sending it to the DPLL for reception. Used to produce FM1 from FM0 and NRZI space from NRZI mark or to invert the data stream in regular NRZ mode. 19-6 MPC8260 PowerQUICC II UserÕs Manual TSNC RINV TINV...
  • Page 563 001 NRZI Mark (set RINV/TINV also for NRZI space). 010 FM0 (set RINV/TINV also for FM1). 011 Reserved. 100 Manchester. 101 Reserved. 110 Differential Manchester (Differential Bi-phase-L). 111 Reserved. MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module Description 19-7...
  • Page 564 0111 Reserved 1000 BISYNC 1001 Reserved 101x Reserved 1100 Ethernet 11xx Reserved 19-8 MPC8260 PowerQUICC II UserÕs Manual Description commands and the E bit of the Rx BD, data provide the CLOSE RXBD , and RESTART TRANSMIT commands, the freeze option...

  • Page 565: Data Synchronization Register (Dsr)

    Field Reset Addr 0x11A0C (TODR1); 0x11A2C (TODR2); 0x11A4C (TODR3); 0x11A6C (TODR4) Figure 19-5. Transmit-on-Demand Register (TODR) MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module Ñ 0000_0000_0000_0000 SYN1...

  • Page 566: Scc Buffer Descriptors (Bds)

    Ñ For a TxBD, this is the number of bytes the controller should send from its buffer. Normally, this value should be greater than zero. The CPM never modiÞes this Þeld. 19-10 MPC8260 PowerQUICC II UserÕs Manual Description C. The user deÞnes how MOTOROLA...
  • Page 567 Figure 19-7 shows the SCC BD table and buffer structure. MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module...
  • Page 568 BD. If E = 0, the current buffer is not empty and it reports a busy error. The CPM does not move from the current BD until E is 19-12 MPC8260 PowerQUICC II UserÕs Manual Tx Buffer Descriptors Status and Control...

  • Page 569: Scc Parameter Ram

    Rx function code. See Section 19.3.2, ÒFunction Code Registers (RFCR and TFCR).Ó 0x05 TFCR Byte Tx function code. See Section 19.3.2, ÒFunction Code Registers (RFCR and TFCR).Ó MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module RESTART TRANSMIT GRACEFUL STOP TRANSMIT command.
  • Page 570 Hword Maximum receive buffer length. DeÞnes the maximum number of bytes the MPC8260 writes to a receive buffer before it goes to the next buffer. The MPC8260 can write fewer bytes than MRBLR if a condition such as an error or end-of-frame occurs. It never writes more bytes than the MRBLR value.

  • Page 571: Scc Base Addresses

    Figure 19-8 shows the register format. Field Ñ Reset Addr SCCx base + 0x04 (RFCRx); SCCx base + 0x05 (TFCRx) Figure 19-8. Function Code Registers (RFCR and TFCR) MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module Address Peripheral 0x8000 SCC1...

  • Page 572: Handling Scc Interrupts

    The SCCM and SCCE bit positions 0x11A74 (SCCM4) are identical. SCCSx SCC status register. This 8-bit, read-only register allows monitoring of the real-time status of RXD. 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4) 19-16 Description Description MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 573: Initializing The Sccs

    An SCC should be disabled and reenabled after any dynamic change to its parallel I/O ports or serial channel physical interface conÞguration. A full reset can also be implemented using CPCR[RST]. MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module...

  • Page 574: Controlling Scc Timing With Rts, Cts, And Cd

    CTS is asserted. Figure 19-10 shows that the delay between CTS and the data can be approximately 0.5 to 1 bit times or 0 bit times, depending on GSMR_H[CTSS]. 19-18 MPC8260 PowerQUICC II UserÕs Manual Last Bit of Frame Data MOTOROLA...
  • Page 575 GSMR_H[CTSS] is zero, the SCC must sample CTS before a CTS lost is recognized; otherwise, the negation of CTS immediately causes the CTS lost condition. See Figure 19-11. MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module...
  • Page 576 CD is sampled on the rising Rx clock edge before data is received. If GSMR_H[CDS] is 1, CD transitions cause data to be immediately gated into the receiver. 19-20 MPC8260 PowerQUICC II UserÕs Manual First Bit of Frame Data CTS Sampled High Here...

  • Page 577: Asynchronous Protocols

    ¥ If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 1, transmission begins in two additional bit times. MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module...

  • Page 578: Digital Phase-Locked Loop (Dpll) Operation

    Figure 19-13 shows the DPLL receiver block; Figure 19-14 shows the transmitter block diagram. RENC RDCR EDGE TSNC RINV HSRCLK RINV HSRCLK Figure 19-13. DPLL Receiver Block Diagram 19-22 MPC8260 PowerQUICC II UserÕs Manual Recovered Clock Carrier SNC DPLL Noise Receiver Hunting Decoded Data RENC ¹ NRZI HSRCLK RCLK 1x Mode...
  • Page 579 ßags or syncs can function as a preamble; others use the patterns in Table 19-8. When transmission occurs, the SCC can generate preamble patterns, as programmed in GSMR_L[TPP, TPL]. MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module...

  • Page 580: Encoding Data With A Dpll

    Each SCC contains a DPLL unit that can be programmed to encode and decode the SCC data as NRZ, NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential Manchester. Figure 19-15 shows the different encoding methods. 19-24 MPC8260 PowerQUICC II UserÕs Manual Preamble Pattern Minimum Preamble Length Required 8-bit...
  • Page 581 A zero is represented by a transition at the center of the bit with the same polarity from the transition at the center of the preceding bit. MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV.

  • Page 582: Clock Glitch Detection

    The SCCs on the MPC8260 have a special circuit designed to detect glitches and alert the system of a problem at the physical layer. The glitch-detect circuit is not a speciÞcation test;...

  • Page 583: Reset Sequence For An Scc Transmitter

    3. Set GSMR_L[ENT, ENR] to enable the SCC with the new protocol. 19.3.9 Saving Power To save power when not in use, an SCC can be disabled by clearing GSMR_L[ENT, ENR]. MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) Part IV. Communications Processor Module...
  • Page 584 Part IV. Communications Processor Module 19-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 585: Scc Uart Mode

    RS-485, which deÞnes a balanced line system allowing longer cables than RS-232 links. Even synchronous protocols like HDLC are sometimes deÞned to run over asynchronous links. The ProÞbus standard extends UART protocol to include LAN- oriented features such as token passing. MOTOROLA Chapter 20. SCC UART Mode 20-1...

  • Page 586: Features

    ¥ Programmable data length (5Ð8 bits) ¥ Programmable fractional stop bit lengths (from 9/16 to 2 bits) in transmission ¥ Capable of reception without a stop bit ¥ Even/odd/force/no parity generation and check 20-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 587: Normal Asynchronous Mode

    PSMR in the same way as in asynchronous mode. When a complete byte has been clocked in, the contents of the MOTOROLA Part IV. Communications Processor Module Chapter 20.

  • Page 588: Scc Uart Parameter Ram

    UADDR1 and UADDR2 with the two preferred addresses. 0x4C RTEMP Hword Temp storage 20-4 MPC8260 PowerQUICC II UserÕs Manual Description command is issued. For 8 data bits, no parity, 1 stop bit, and 1 start bit, ) counters incremented by the CP. STOP...

  • Page 589: Data-Handling Methods: Character- Or Message-Based

    In a message-based environment, transfers can be made on entire messages rather than on individual characters. To simplify programming and save processor overhead, a message is transferred as a linked list of buffers without core intervention. For example, before MOTOROLA Part IV. Communications Processor Module Chapter 20. SCC UART Mode...

  • Page 590: Error And Status Reporting

    Resets the transmit parameters in the parameter RAM. Issue only when the transmitter is disabled. INIT TX Note that PARAMETERS INIT TX AND RX PARAMETERS 20-6 MPC8260 PowerQUICC II UserÕs Manual Description STOP TRANSMIT as a message is being sent, the message is aborted. The transmitter command, after a GRACEFUL STOP TRANSMIT resets both Tx and Rx parameters.

  • Page 591: Multidrop Systems And Address Recognition

    ¥ Manual multidrop modeÑThe controller receives all characters. An address character is always written to a new buffer and can be followed by data characters. User software performs the address comparison. MOTOROLA Part IV. Communications Processor Module Description functions like...

  • Page 592: Receiving Control Characters

    The 16-bit entries in the control character table support control character recognition. Each entry consists of the control character, a valid bit (end of table), and a reject bit. See Figure 20-3. 20-8 MPC8260 PowerQUICC II UserÕs Manual Slave 1 Slave 2 Slave 3...
  • Page 593 (R = 1), the PIP controller writes the character into the RCCR and generates a maskable interrupt. If the core does not process the interrupt and read RCCR before a new control character arrives, the previous control character is overwritten. MOTOROLA Part IV. Communications Processor Module Ñ Ñ...

  • Page 594: Hunt Mode (Receiver)

    CTS negates when the TOSEQ character is sent. If CTS negates and the TOSEQ character is sent during a buffer transmission, the TxBD[CT] status bit is also set. 20-10 MPC8260 PowerQUICC II UserÕs Manual ENTER HUNT MODE Ñ...

  • Page 595: Sending A Break (Transmitter)

    Idle characters are always sent as full-length characters. Field Ñ Reset 1111 Addr Figure 20-5. Asynchronous UART Transmitter MOTOROLA Part IV. Communications Processor Module Description Ñ Ñ Ñ Ñ Ñ Chapter 20. SCC UART Mode...

  • Page 596: Handling Errors In The Scc Uart Controller

    Note that if CTS is used, the UART also offers an asynchronous ßow control option that does not generate an error. See the description of PSMR[FLC] in Table 20-9. 20-12 MPC8260 PowerQUICC II UserÕs Manual Description Description command is issued and CTS is asserted.

  • Page 597: Uart Mode Register (Psmr)

    For UART mode, the SCC protocol-speciÞc mode register (PSMR) is called the UART mode register. Many bits can be modiÞed while the receiver and transmitter are enabled. Figure 20-6 shows the PSMR in UART mode. MOTOROLA Part IV. Communications Processor Module Table 20-8. Reception Errors Description Chapter 20.
  • Page 598 1 The SCC completes transmission of any data already transferred to the Tx FIFO (the number of characters depends on GSMR_H[TFL]) and then freezes. After FRZ is cleared, transmission resumes from the next character. 20-14 MPC8260 PowerQUICC II UserÕs Manual FRZ RZS SYN DRT Description Ñ...

  • Page 599: Scc Uart Receive Buffer Descriptor (Rxbd)

    ¥ A user-deÞned control character is received. ¥ An error occurs during message processing. ¥ A full receive buffer is detected. ¥ A MAX_IDL number of consecutive idle characters is received. MOTOROLA Part IV. Communications Processor Module Description Chapter 20. SCC UART Mode...
  • Page 600 32-Bit Buffer Pointer 10 Characters Characters Received by UART Time Figure 20-7. SCC UART Receiving using RxBDs 20-16 MPC8260 PowerQUICC II UserÕs Manual command is issued. CLOSE RXBD MRBLR = 8 Bytes for this SCC Buffer Full Idle Time-Out Occurred...
  • Page 601 PSMR[UM]. After an address match, AM identiÞes which user-deÞned address character was matched. 0 The address matched the value in UADDR2. 1 The address matched the value in UADDR1. Ñ Reserved, should be cleared. MOTOROLA Part IV. Communications Processor Module Ñ Data Length Rx Buffer Pointer Description Chapter 20.

  • Page 602: Scc Uart Transmit Buffer Descriptor (Txbd)

    1 Last BD in the table. After this buffer is used, the CPM sends data using the BD pointed to by TBASE. The number of TxBDs in this table is determined only by the W bit and space constraints of the dual-port RAM. 20-18 MPC8260 PowerQUICC II UserÕs Manual Description Data Length Tx Buffer Pointer Description Ñ...

  • Page 603: Scc Uart Event Register (Scce) And Mask Register (Sccm)

    SCCE. Setting a mask bit enables the corresponding SCCE interrupt; clearing a bit masks it. Figure 20-10 shows example interrupts that can be generated by the SCC UART controller. MOTOROLA Part IV. Communications Processor Module Description Chapter 20.
  • Page 604 0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4) 0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4) Figure 20-11. SCC UART Event Register (SCCE) and Mask Register (SCCM) 20-20 MPC8260 PowerQUICC II UserÕs Manual 10 Characters Line Idle 7 Characters Ñ...

  • Page 605: Scc Uart Status Register (Sccs)

    The SCC UART status register (SCCS), shown in Figure 20-12, monitors the real-time status of RXD. Field Reset Addr 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4) Figure 20-12. SCC Status Register for UART Mode (SCCS) MOTOROLA Part IV. Communications Processor Module Description Ñ 0000_0000_0000_0000 Chapter 20. SCC UART Mode GRACEFUL...

  • Page 606: Scc Uart Programming Example

    12. Clear PAREC, FRMEC, NOSEC, and BRKEC in parameter RAM. 13. Clear UADDR1 and UADDR2. They are not used. 14. Clear TOSEQ. It is not used. 20-22 MPC8260 PowerQUICC II UserÕs Manual Description INIT RX AND TX PARAMS commands send only one break character.

  • Page 607: S-Records Loader Application

    S-record Þts into a single buffer. Follow the basic UART initialization sequence above in Section 20.21, ÒSCC UART Programming Example,Ó except allow for more and larger buffers and create the control character table as described in Table 20-14. MOTOROLA Part IV. Communications Processor Module Chapter 20. SCC UART Mode...
  • Page 608 TxBD table; transmission can be paused when an XOFF character is received. This scheme minimizes the number of interrupts the core receives (one per S- record) and relieves it from continually scanning for control characters. 20-24 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 609: Scc Hdlc Mode

    TDM channels of the serial interface (SI). In HDLC mode, an SCC becomes an HDLC controller, and consists of separate transmit and receive sections whose operations are asynchronous with the core and can either be synchronous or asynchronous with respect to other SCCs. MOTOROLA Chapter 21. SCC HDLC Mode 21-1...

  • Page 610: Scc Hdlc Features

    When the SCC receives a command, it sends idles or ßags instead of the current frame until it receives a TRANSMIT command. The RESTART TRANSMIT 21-2 MPC8260 PowerQUICC II UserÕs Manual Control Information (Optional) 8 bits 8n bits GRACEFUL STOP TRANSMIT...

  • Page 611: Scc Hdlc Channel Frame Reception

    Rx FIFO delay. 21.4 SCC HDLC Parameter RAM For HDLC mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in Table 21-1. MOTOROLA Chapter 21. SCC HDLC Mode 21-3...
  • Page 612 See Figure 21-2. 0x58 Hword Temporary storage. 0x5A TMP_MB Hword Temporary storage. From SCC base. See Section 19.3.1, ÒSCC Base Addresses.Ó 21-4 Description counters maintained by the CP. Initialize them while the channel is MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 613: Programming The Scc In Hdlc Mode

    The transmitter resumes from the current BD. Resets the Tx parameters in the parameter RAM. Issue only when the transmitter is disabled. INIT TX resets both Tx and Rx parameters. PARAMETERS RX PARAMETERS MOTOROLA Part IV. Communications Processor Module Control etc. 0xAA 0x44...

  • Page 614: Handling Errors In The Scc Hdlc Controller

    RXF interrupt if not masked. The rest of the frame is lost and other errors are not Reception checked in that frame. At this point, the receiver enters hunt mode. 21-6 MPC8260 PowerQUICC II UserÕs Manual Description ENTER HUNT MODE resets both Tx and Rx parameters.

  • Page 615: Hdlc Mode Register (Psmr)

    10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1. MOTOROLA Part IV. Communications Processor Module...

  • Page 616: Scc Hdlc Receive Buffer Descriptor (Rxbd)

    The CP uses the RxBD, shown in Figure 21-4, to report on data received for each buffer. Offset + 0 Ñ Offset + 2 Offset + 4 Offset + 6 Figure 21-4. SCC HDLC Receive Buffer Descriptor (RxBD) 21-8 MPC8260 PowerQUICC II UserÕs Manual Description Ñ Ñ Data Length Rx Buffer Pointer MOTOROLA...
  • Page 617 Carrier detect lost (NMSI mode only). Set when CD is negated during frame reception. Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer Descriptors (BDs).Ó Because HDLC is a frame-based protocol, RxBD[Data Length] of the MOTOROLA Part IV. Communications Processor Module Description Chapter 21.
  • Page 618 C = Control byte I = Information byte CR = CRC Byte Figure 21-5. SCC HDLC Receiving Using RxBDs 21-10 MPC8260 PowerQUICC II UserÕs Manual MRBLR = 8 Bytes for this SCC Buffer full Buffer closed when closing flag Received...

  • Page 619: Scc Hdlc Transmit Buffer Descriptor (Txbd)

    CTS lost. Indicates when CTS in NMSI mode or layer 1 grant is lost in GCI or IDL mode during frame transmission. If data from more than one buffer is currently in the FIFO when this error occurs, the HDLC writes CT in the current BD after sending the buffer. MOTOROLA Part IV. Communications Processor Module Data Length...

  • Page 620: Hdlc Event Register (Scce)/Hdlc Mask Register (Sccm)

    9Ð10 Ñ Reserved, should be cleared. Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel. 21-12 MPC8260 PowerQUICC II UserÕs Manual GLT DCC FLG 0000_0000_0000_0000 Description command completed execution. Set as soon as GRACEFUL STOP TRANSMIT Ñ...
  • Page 621 2. Example shows one additional opening flag. This is programmable. 3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself. Figure 21-8. SCC HDLC Interrupt Event Example MOTOROLA Part IV. Communications Processor Module Description...

  • Page 622: Scc Hdlc Status Register (Sccs)

    0 is received. 21.13 SCC HDLC Programming Examples The following sections show examples for programming SCCs in HDLC mode. The Þrst example uses an external clock. The second example implements Manchester encoding. 21-14 MPC8260 PowerQUICC II UserÕs Manual Ñ 0000_0000 Description MOTOROLA...

  • Page 623: Scc Hdlc Programming Example #1

    18. Initialize the RxBD. Assume the buffer is at 0x0000_1000 in main memory. RxBD[Status and Control]= 0xB000, RxBD[Data Length] = 0x0000 (not required), and RxBD[Buffer Pointer] = 0x0000_1000. MOTOROLA Part IV. Communications Processor Module INIT RX AND TX PARAMS Chapter 21. SCC HDLC Mode...

  • Page 624: Scc Hdlc Programming Example #2

    CRC and to reject multiple frames in the FIFO. 4. Write 0x004A_A430 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write to GSMR_L2 ensures that ENT and ENR are enabled last. 21-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 625: Hdlc Bus Mode With Collision Detection

    The collision-detection mechanism supports only: ¥ NRZ-encoded data ¥ A common synchronous clock for all receivers and transmitters ¥ Non-inverted data (GSMR[RINV, TINV] = 0) ¥ Open-drain connection with no external transceivers MOTOROLA Part IV. Communications Processor Module Chapter 21. SCC HDLC Mode 21-17...
  • Page 626 The beneÞt of this conÞguration, however, is that full-duplex operation can be obtained. In a point-to-multipoint environment, this is the preferred conÞguration. Figure 21-11 shows the single-master conÞguration. 21-18 MPC8260 PowerQUICC II UserÕs Manual HDLC Bus LAN HDLC Bus HDLC Bus...

  • Page 627: Hdlc Bus Features

    CTS. CTS is sampled halfway through the bit time using the rising edge of the Tx clock. If the transmitted bit matches the received CTS bus sample, transmission continues. However, if the received CTS sample is 0 and the transmitted bit is 1, MOTOROLA Part IV. Communications Processor Module HDLC Bus LAN...

  • Page 628: Increasing Performance

    To increase performance, give the one bit more rise time by using a clock that is low longer than it is high, as shown in Figure 21-13. 21-20 MPC8260 PowerQUICC II UserÕs Manual CTS sampled at halfway point. Collision detected when TXD=1, but CTS=0.

  • Page 629: Delayed Rts Mode

    RTS can be used to enable the output of the line driver. As a result, the electrical effects of collisions are isolated locally. Figure 21-15 shows RTS timing. MOTOROLA Part IV. Communications Processor Module CTS sampled at three quarter point.

  • Page 630: Using The Time-Slot Assigner (Tsa)

    CTS pin, it must be conÞgured to connect to the chosen SCC. Because the SCC only receives clocks during its time slot, CTS is sampled only during the Tx clock edges of the particular SCC time slot. 21-22 MPC8260 PowerQUICC II UserÕs Manual Collision 1st Bit 2nd Bit...

  • Page 631: Hdlc Bus Protocol Programming

    21.14.6 HDLC Bus Protocol Programming The HDLC bus on the MPC8260 is implemented using the SCC in HDLC mode with bus- speciÞc options selected in the PSMR and GSMR, as outlined below. See also Section 21.5, ÒProgramming the SCC in HDLC Mode.Ó...
  • Page 632 Part IV. Communications Processor Module 21-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 633: Scc Bisync Mode

    In nontransparent operation, the receiver discards additional synchronization characters (SYNCs) as they are received. In transparent mode, DLE-SYNC pairs are discarded. Normally, for proper MOTOROLA Nontransparent with Header Header...

  • Page 634: Features

    Part IV. Communications Processor Module transmission, an underrun must not occur between the DLE and its following character. This failure mode cannot occur with the MPC8260. An SCC can be conÞgured as a BISYNC controller to handle basic BISYNC protocol in normal and transparent modes.

  • Page 635: Scc Bisync Channel Frame Reception

    Note that GSMR_H[RFW] should be set for an 8-bit-wide receive FIFO for the BISYNC receiver. See Section 19.1.1, ÒThe General SCC Mode Registers (GSMR1ÐGSMR4).Ó 22.4 SCC BISYNC Parameter RAM For BISYNC mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in Table 22-1. MOTOROLA Chapter 22. SCC BISYNC Mode 22-3...
  • Page 636 ¥ The controller can be programmed so software handles the Þrst two or three bytes. The controller directly handles subsequent data without interrupting the core. 22-4 MPC8260 PowerQUICC II UserÕs Manual Description Reserved CRC constant temp value.

  • Page 637: Scc Bisync Commands

    Initializes receive parameters in this serial channelÕs parameter RAM to reset state. Issue only when INIT RX the receiver is disabled. An PARAMETERS MOTOROLA Part IV. Communications Processor Module Description is issued. command is issued, after a transmitter error occurs, or after a resets transmit and receive parameters.

  • Page 638: Scc Bisync Control Character Recognition

    The RCCM entry deÞnes classes of control characters that support masking option. Offset from SCCx Base 0x42 0x44 0x46 0x48 0x4A 0x4D 0x4E 0x50 0x52 Figure 22-2. Control Character Table and RCCM 22-6 MPC8260 PowerQUICC II UserÕs Manual Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ CHARACTER1 CHARACTER2 CHARACTER3 CHARACTER4...

  • Page 639: Bisync Sync Register (Bsync)

    (BSYNC[V]) is set.When using 7-bit characters with parity, the parity bit should be included in the SYNC register value. Field Reset Address Figure 22-3. BISYNC SYNC (BSYNC) MOTOROLA Part IV. Communications Processor Module Description UndeÞned SCC Base + 0x3E Chapter 22. SCC BISYNC Mode...

  • Page 640: Scc Bisync Dle Register (Bdle)

    When using 7-bit characters with parity, the parity bit should be included in the DLE register value. Field Reset Address Figure 22-4. BISYNC DLE (BDLE) 22-8 MPC8260 PowerQUICC II UserÕs Manual Description UndeÞned SCC Base + 0x40 MOTOROLA...

  • Page 641: Sending And Receiving The Synchronization Sequence

    22.10 Handling Errors in the SCC BISYNC The controller reports message transmit and receive errors using the channel BDs, error counters, and the SCCE. Modem lines can be directly monitored via the parallel port pins. MOTOROLA Part IV. Communications Processor Module Description...

  • Page 642: Bisync Mode Register (Psmr)

    RTR, RPM, TPM] can be modiÞed on-the-ßy. Field Reset Addr 0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4) Figure 22-5. Protocol-Specific Mode Register for BISYNC (PSMR) 22-10 MPC8260 PowerQUICC II UserÕs Manual Transmit Errors Table 22-8. Description RESTART TRANSMIT RESTART TRANSMIT Receive Errors Table 22-9.
  • Page 643 BISYNC channel is being conÞgured onto a multidrop line and the user does not want to receive its own transmission. Although BISYNC usually uses a half-duplex protocol, the receiver is not actually disabled during transmission. 10Ð11 Ñ Reserved, should be cleared. MOTOROLA Part IV. Communications Processor Module Description Chapter 22. SCC BISYNC Mode 22-11...

  • Page 644: Scc Bisync Receive Bd (Rxbd)

    RxBD. The CP does not use this BD as long as the E bit is zero. 1 The buffer is not full. The CP controls this BD and buffer. The core should not update this BD. 22-12 MPC8260 PowerQUICC II UserÕs Manual Description command is issued.
  • Page 645 Descriptors (BDs).Ó Data length represents the number of octets the CP writes into this buffer, including the BCS. For BISYNC mode, clear these bits. It is incremented each time a received character is written to the buffer. MOTOROLA Part IV. Communications Processor Module Description Chapter 22.

  • Page 646: Scc Bisync Transmit Bd (Txbd)

    BCS reset. Determines whether transmitter BCS accumulation is reset before sending the data buffer. 0 BCS accumulation is not reset. 1 BCS accumulation is reset before sending the data buffer. 22-14 MPC8260 PowerQUICC II UserÕs Manual Data Length Tx Data Buffer Pointer Description Ñ...

  • Page 647: Bisync Event Register (Scce)/Bisync Mask Register (Sccm)

    GLR GLT DCC Reset Addr 0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4) 0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4) Figure 22-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) MOTOROLA Part IV. Communications Processor Module Description Ñ Ñ 0000_0000_0000_0000 Chapter 22.

  • Page 648: Scc Status Registers (Sccs)

    CTS and CD are part of the parallel I/O. Field Reset Addr 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4) Figure 22-9. SCC Status Registers (SCCS) 22-16 MPC8260 PowerQUICC II UserÕs Manual Description is issued (immediately if no message is in progress). command. Ñ 0000_0000 Ñ...

  • Page 649: Programming The Scc Bisync Controller

    Using Table 22-15, the control character table should be set to recognize the end of the block. MOTOROLA Part IV. Communications Processor Module Description command. For example, if a DLE-STX is RESET BCS CALCULATION Chapter 22.

  • Page 650: Scc Bisync Programming Example

    10. Write PRCRC with 0x0000 to comply with CRC16. 11. Write PTCRC with 0x0000 to comply with CRC16. 12. Clear PAREC for clarity. 22-18 MPC8260 PowerQUICC II UserÕs Manual Control Characters INIT RX AND TX PARAMETERS . This updates MOTOROLA...
  • Page 651 TxBD is closed. The buffer is closed after 16 bytes are received. Any received data beyond 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MOTOROLA Part IV. Communications Processor Module Chapter 22. SCC BISYNC Mode...
  • Page 652 Part IV. Communications Processor Module 22-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 653: Scc Transparent Mode

    The following list summarizes the main features of the SCC in transparent mode: ¥ Flexible buffers ¥ Automatic SYNC detection on receive ¥ CRCs can be sent and received ¥ Reverse data mode MOTOROLA Chapter 23. SCC Transparent Mode 23-1...

  • Page 654: Scc Transparent Channel Frame Transmission Process

    When the core enables the SCC receiver in transparent mode, it waits to achieve synchronization before data is received. The receiver can be synchronized to the data by a synchronization pulse or SYNC pattern. 23-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 655: Achieving Synchronization In Transparent Mode

    If a 4-bit SYNC is selected, reception begins as soon as these four bits are received, beginning with the Þrst bit following the 4-bit SYNC. The transmitter synchronizes on the receiver pattern if GSMR_H[RSYN] = 1. MOTOROLA Part IV. Communications Processor Module Bit Assignments...

  • Page 656: External Synchronization Signals

    It is also an option to link the transmitter synchronization to the receiver synchronization. Diagrams for the pulse/envelope and sampling options are shown in Section 23.4, ÒAchieving Synchronization in Transparent Mode.Ó 23.4.1.2.1 External Synchronization Example Figure shows synchronization using external signals. 23-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 657: Transparent Mode Without Explicit Synchronization

    (Output is CD Input) Notes: 1. Each MPC8260 generates its own transmit clocks. If the transmit and receive clocks are the same, one MPC8260 can generate transmit and receive clocks for the other MPC8260. For example, CLKx on MPC8260 (B) could be used to clock the transmitter and receiver.

  • Page 658: Inline Synchronization Pattern

    The optional reversal of data (GSMR_H[REVD] = 1) is done just before data is stored in memory (after the CRC calculation). 23.6 SCC Transparent Parameter RAM For transparent mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in Table 23-2. 23-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 659: Scc Transparent Commands

    TBPTR in the channel TxBD table. Initializes all transmit parameters in the serial channel parameter RAM to reset state. Issue only when INIT TX the transmitter is disabled. PARAMETERS MOTOROLA Part IV. Communications Processor Module Description Description RESTART TRANSMIT command is issued (at which point the channel is disabled in SCCM), after a command is issued, or after a transmitter error.

  • Page 660: Handling Errors In The Transparent Controller

    Reception is lost, and no other errors are checked in the message. The receiver immediately enters hunt mode. 23-8 MPC8260 PowerQUICC II UserÕs Manual Description forces the transparent receiver to the current ENTER HUNT MODE resets receive and transmit parameters.

  • Page 661: Transparent Mode And The Psmr

    1 Last BD in the table. After this buffer is used, the CPM receives data into the Þrst BD that RBASE points to. The number of BDs in this table is determined only by RxBD[W] and overall space constraints of the dual-port RAM. MOTOROLA Part IV. Communications Processor Module command is Issued.

  • Page 662: Scc Transparent Transmit Buffer Descriptor (Txbd)

    TxBD table. The CPM uses BDs to conÞrm transmission or indicate error conditions so the processor knows buffers have been serviced. Prepare status and control bits before transmission; they are set by the CPM after the buffer is sent. 23-10 MPC8260 PowerQUICC II UserÕs Manual Descriptions (Continued) Description MOTOROLA...
  • Page 663 Ñ Reserved, should be cleared. Underrun. Set when the SCC encounters a transmitter underrun condition while sending the buffer. CTS lost. Indicates the CTS was lost during frame transmission. MOTOROLA Part IV. Communications Processor Module Data Length Tx Buffer Pointer Description Chapter 23.

  • Page 664: Scc Transparent Event Register (Scce)/Mask Register (Sccm)

    9Ð10 Ñ Reserved, should be cleared. Tx error. Set when an error occurs on the transmitter channel. Ñ Reserved, should be cleared. 23-12 MPC8260 PowerQUICC II UserÕs Manual Ñ Ñ 0000_0000_0000_0000 Description GRACEFUL STOP TRANSMIT Ñ...

  • Page 665: Scc Status Register In Transparent Mode (Sccs)

    23.14 SCC2 Transparent Programming Example The following initialization sequence enables the transmitter and receiver, which operate independently of each other. They implement the connection shown on MPC8260(B) in Figure 23-1. The transmit and receive clocks are externally provided to MPC8260(B) using CLK3.
  • Page 666 20. Write 0x0000_0030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write ensures that the ENT and ENR bits are enabled last. 23-14 MPC8260 PowerQUICC II UserÕs Manual INIT RX AND TX PARAMETERS INIT RX AND TX PARAMETERS for SCC2.
  • Page 667 Note that after 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MOTOROLA Chapter 23. SCC Transparent Mode 23-15...
  • Page 668 Part IV. Communications Processor Module 23-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 669: Scc Ethernet Mode

    LAN; if one is found, the station forces a jam pattern (all ones) on its frame and stops sending. Most collisions occur close to the beginning of a frame. The station waits MOTOROLA Chapter 24. SCC Ethernet Mode...

  • Page 670: Ethernet On The Mpc8260

    EEST instead. The on-chip DPLL cannot be used for low-speed (1-Mbps) Ethernet either because it cannot properly detect start-of-frame or end-of-frame. Note that the CPM of the MPC8260 requires a minimum system clock frequency of 24 MHz to support Ethernet.

  • Page 671: Features

    ¥ Up to eight parallel I/O pins can be sampled and appended to any frame ¥ Optional heartbeat indication ¥ Transmitter network management and diagnostics Ñ Lost carrier sense Ñ Underrun Ñ Number of collisions exceeded the maximum allowed MOTOROLA Part IV. Communications Processor Module Chapter 24. SCC Ethernet Mode 24-3...

  • Page 672: Connecting The Mpc8260 To Ethernet

    MPC8260. ¥ Transmit clock (TCLK)Ña CLKx signal routed through the bank of clocks on the MPC8260. Note that RCLK and TCLK should not be connected to the same CLKx since the SIA provides separate transmit and receive clock signals. ¥ Transmit data (TXD)Ñthe MPC8260 TXD signal.

  • Page 673: Scc Ethernet Channel Frame Transmission

    NOTE: Short Tx frames are padded automatically by the MPC8260. Figure 24-3. Connecting the MPC8260 to Ethernet The EEST has similar names for its connection to the above seven MPC8260 signals. The EEST also provides a loopback input so the MPC8260 can perform external loopback testing, which can be controlled by any available MPC8260 parallel I/O signal.

  • Page 674: Scc Ethernet Channel Frame Reception

    When the incoming pattern is not rejected and matches the DSR, the SFD has been detected; hunt mode is terminated and character assembly begins. When the receiver detects the Þrst bytes of the frame, the Ethernet controller performs 24-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 675: The Content-Addressable Memory (Cam) Interface

    CAM. See Section 24.10, ÒSCC Ethernet Address Recognition.Ó The MPC8260 outputs a receive start (RSTRT) signal when the start frame delimiter is recognized. This signal is asserted for one bit time on the second destination address bit.

  • Page 676: Scc Ethernet Parameter Ram

    0x52 MAXD Hword Rx max DMA. 0x54 DMA_CNT Hword Rx DMA counter. A temporary down-counter used to track frame length. 24-8 MPC8260 PowerQUICC II UserÕs Manual Description ) counters that can be initialized while the channel is disabled. MOTOROLA...
  • Page 677 0x98 IADDR3 0x9A IADDR4 0x9C BOFF_CNT Hword Backoff counter. MOTOROLA Part IV. Communications Processor Module Description command is used to enable the hash table. command is used to enable the hash table. SET GROUP ADDRESS Chapter 24. SCC Ethernet Mode...

  • Page 678: Programming The Ethernet Controller

    Initializes transmit parameters in this serial channel parameter RAM to reset state. Issue only when the INIT TX transmitter is disabled. PARAMETERS 24-10 MPC8260 PowerQUICC II UserÕs Manual Description Description command is issued. is issued and the current frame ends in a collision, TBPTR points command is issued or a transmitter error.

  • Page 679: Scc Ethernet Address Recognition

    Þeld of the received frame with the user-programmed physical address in PADDR1. Address recognition can be performed on multiple individual addresses using the IADDR1Ð4 hash table. MOTOROLA Part IV. Communications Processor Module Description command is generally used to force the Ethernet receiver to resets receive and transmit parameters.
  • Page 680 REJECT while the frame is being received. The on-chip address recognition functions can be used in addition to the external CAM address recognition functions. 24-12 MPC8260 PowerQUICC II UserÕs Manual Check Address I/G Address Broadcast...

  • Page 681: Hash Table Algorithm

    (512 bit times or 52 µs). If a collision occurs after 64 byte times, no retransmission is performed and the buffer is closed with an LC error indication. MOTOROLA Chapter 24. SCC Ethernet Mode...

  • Page 682: Internal And External Loopback

    When this error occurs, the channel stops sending the buffer, closes it, sets SCCE[TXE] and the LC bit in the TxBD. The channel resumes transmission after it receives the command. This error is discussed further in the deÞnition of PSMR[LCW]. TRANSMIT 24-14 MPC8260 PowerQUICC II UserÕs Manual Description command. RESTART TRANSMIT RESTART TRANSMIT command.

  • Page 683: Ethernet Mode Register (Psmr)

    This heartbeat condition does not imply a collision error, but that the transceiver seems to be functioning properly. If SCCE[HBC] = 1 and the MPC8260 does not detect a heartbeat condition after sending a frame, a heartbeat error occurs; the channel closes the buffer, sets the HB bit in the TxBD, and generates the TXE interrupt if it is enabled.
  • Page 684 Force collision. 0 Normal operation. 1 The channel forces a collision when each frame is sent. To test collision logic conÞgure the MPC8260 in loopback operation. In the end, the retry limit for each transmit frame is exceeded. Receive short frames.

  • Page 685: Scc Ethernet Receive Bd

    0 No SCCE[RXB] interrupt is generated after this buffer is used. 1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the Ethernet controller. These two bits can cause interrupts if they are enabled. MOTOROLA Part IV. Communications Processor Module Description Ñ...
  • Page 686 Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer Descriptors (BDs).Ó Data length includes the total number of frame octets (including four bytes for CRC). Figure 24-7 shows an example of how RxBDs are used in receiving. 24-18 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 687: Scc Ethernet Transmit Buffer Descriptor

    24.19 SCC Ethernet Transmit Buffer Descriptor Data is sent to the Ethernet controller for transmission on an SCC channel by arranging it in buffers referenced by the channel TxBD table. The Ethernet controller uses TxBDs to MOTOROLA Part IV. Communications Processor Module Buffer Full Buffer Closed after CRC Received.
  • Page 688 Late collision. Set when a collision occurred after the number of bytes deÞned for PSMR[LCW] are sent. The Ethernet controller stops sending and writes this bit after it Þnishes sending the buffer. 24-20 MPC8260 PowerQUICC II UserÕs Manual Data Length Tx Data Buffer Pointer...

  • Page 689: Scc Ethernet Event Register (Scce)/Mask Register (Sccm)

    Bits Name 0Ð7 Ñ Reserved, should be cleared. Graceful stop complete. Set as soon the transmitter Þnishes any frame that was in progress when a GRACEFUL STOP TRANSMIT MOTOROLA Part IV. Communications Processor Module Description Ñ 0000_0000_0000_0000 Description command was issued. It is set immediately if no frame was in progress.
  • Page 690 P = Preamble, SFD = Start frame delimiter, DA and SA = Source/Destination address, T/L = Type/Length, D = Data, CR = CRC bytes Figure 24-10. Ethernet Interrupt Events Example 24-22 MPC8260 PowerQUICC II UserÕs Manual Description Stored in Rx Buffer Stored in Tx Buffer TXB, GRA command was issued during frame transmission.

  • Page 691: Scc Ethernet Programming Example

    19. Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. MOTOROLA Part IV. Communications Processor Module INIT RX AND TX PARAMETERS Chapter 24.
  • Page 692 Ethernet mode. TCI is set to allow more setup time for the EEST to receive the MPC8260 transmit data. TPL and TPP are set for Ethernet requirements. The DPLL is not used with Ethernet. Note that the ENT and ENR are not enabled yet.

  • Page 693: Scc Appletalk Mode

    LocalTalk physical and link-layer protocol, an HDLC-based protocol that runs at 230.4 kbps. In this manual, the term ÔAppleTalk controllerÕ refers to the support that the MPC8260 provides for LocalTalk protocol. The AppleTalk controller provides required frame synchronization, bit sequence, preamble, and postamble onto standard HDLC frames.

  • Page 694: Features

    ¥ Automatic postamble transmission ¥ Reception of sync sequence does not cause extra SCCE[DCC] interrupts ¥ Reception is automatically disabled while sending a frame ¥ Transmit-on-demand feature expedites frames ¥ Connects directly to an RS-422 transceiver 25-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 695: Connecting To Appletalk

    25.3 Connecting to AppleTalk As shown in Figure , the MPC8260 connects to LocalTalk, and, using TXD, RTS, and RXD, is an interface for the RS-422 transceiver. The RS-422, in turn, is an interface for the LocalTalk connector. Although it is not shown, a passive RC circuit is recommended between the transceiver and connector.

  • Page 696: Programming The Psmr

    Use the transmit-on-demand (TODR) register to expedite a transmit frame. See Section 19.1.4, ÒTransmit-on-Demand Register (TODR).Ó 25.4.4 SCC AppleTalk Programming Example Except for the previously discussed register programming, use the example in Section 21.14.6, ÒHDLC Bus Protocol Programming.Ó 25-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 697: Serial Management Controllers (Smcs)

    The SMC receiver and transmitter are double-buffered, corresponding to an effective FIFO size (latency) of two characters. Chapter 14, ÒSerial Interface with Time-Slot Assigner,Ó describes GCI interface conÞguration. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-1...

  • Page 698: Features

    ¥ Each SMC channel fully supports the C/I and monitor channels of the GCI (IOM-2) in ISDN applications ¥ Two SMCs support the two sets of C/I and monitor channels in the SCIT channels 0 and 1 26-2 MPC8260 PowerQUICC II UserÕs Manual 60x Bus Control Control Registers...

  • Page 699: Smc Mode Registers (Smcmr1/Smcmr)

    Bits 0Ð7 vary according to protocol selected by the SM bits. Field: UART Ñ CLEN Transparent Reset Address Figure 26-2. SMC Mode Registers (SMCMR1/SMCMR2) MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module Ñ Ñ REVD Ñ 0000_0000_0000_0000...
  • Page 700 1 Reverse the character bit order. The msb is sent Þrst. SCIT channel number. (GCI) 0 SCIT channel 0 1 SCIT channel 1. Required for Siemens ARCOFI and SGS S/T chips. 8Ð9 Ñ Reserved, should be cleared. 26-4 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 701: Smc Buffer Descriptor Operation

    SMC RxBD Table Pointer to SMCx RxBD Table Pointer to SMCx TxBD Table Figure 26-3. SMC Memory Structure MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module Description External Memory TxBD Table Status and Control Data Length...

  • Page 702: Smc Parameter Ram

    0x06 MRBLR Hword Maximum receive buffer length. The most bytes the MPC8260 writes to a receive buffer before moving to the next buffer. It can write fewer bytes than MRBLR if a condition like an error or end-of-frame occurs, but it cannot exceed MRBLR. MPC8260 buffers should not be smaller than MRBLR.
  • Page 703 From the pointer value programmed in SMCx_BASE: SMC1_BASE at 0x87FC, SMC2_BASE at IMMR + 0x88FC. Not accessed for normal operation. May hold helpful information for experienced users and for debugging. To extract data from a partially full receive buffer, issue a MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module...

  • Page 704: Smc Function Code Registers (Rfcr/Tfcr)

    MSB of the same double word. 1x Motorola (big-endian) byte ordering (normal operation). As data is sent onto the serial line from the buffer, the MSB of the buffer word contains data to be sent earlier than the LSB of the same word.

  • Page 705: Disabling Smcs On-The-Fly

    CLOSE RXBD 4. Set SMCMR[REN]. Reception immediately uses the RxBD that RBPTR pointed to if E is set in the RxBD. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module command to stop transmission STOP TRANSMIT...

  • Page 706: Smc Receiver Shortcut Sequence

    ¥ SCCS register to determine idle status of the receive signal ¥ Other features for the SCCs as described in the GSMR 26-10 MPC8260 PowerQUICC II UserÕs Manual command and make any additional changes. to initialize transmit and receive MOTOROLA...

  • Page 707: Features

    CP accesses this buffer. For instance, if a single TxBD is initialized with the CM and W bits set, the buffer is sent continuously until R is cleared in the BD. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV.

  • Page 708: Smc Uart Channel Reception Process

    Initializes transmit parameters in this serial channelÕs parameter RAM to their reset state and should INIT TX only be issued when the transmitter is disabled. The PARAMETERS used to reset the transmit and receive parameters. 26-12 MPC8260 PowerQUICC II UserÕs Manual Description command. The SMC UART STOP TRANSMIT command can also be INIT TX...

  • Page 709: Sending A Break

    Receive no receive buffer is open, this does not generate an interrupt or any status information. The idle counter is reset each time a character is received. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module command instead ENTER HUNT MODE resets both receive and transmit parameters.

  • Page 710: Smc Uart Rxbd

    1 The SMCE[RXB] is set when this buffer is completely Þlled by the CP, indicating the need for the core to process the buffer. RXB can cause an interrupt if it is enabled. 26-14 MPC8260 PowerQUICC II UserÕs Manual Description Ñ...
  • Page 711 Figure 26-7 shows the UART RxBD process, showing RxBDs after they receive 10 characters, an idle period, and Þve characters (one with a framing error). The example assumes that MRBLR = 8. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module...

  • Page 712: Smc Uart Txbd

    TxBD table. Using the BDs, the CP confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced. 26-16 MPC8260 PowerQUICC II UserÕs Manual MRBLR = 8 Bytes for this SMC Buffer Full...
  • Page 713 Tx data buffer pointer points to the Þrst location of the buffer. It can be even or odd, unless the number of data bits in the UART character is greater than 8 bits. Then the buffer pointer MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV.

  • Page 714: Smc Uart Event Register (Smce)/Mask Register (Smcm)

    Figure 26-10 shows an example of the timing of various events in the SMCE. 26-18 MPC8260 PowerQUICC II UserÕs Manual Ñ Ñ Description...

  • Page 715: Smc Uart Controller Programming Example

    7. Write RFCR and TFCR with 0x10 for normal operation. 8. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16 bytes, so MRBLR = 0x0010. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module...

  • Page 716: Smc In Transparent Mode

    ¥ Ability to transmit data on demand using the TODR ¥ Receiver/transmitter in transparent mode while executing another protocol ¥ 4-, 8-, or 16-bit SYNC recognition ¥ Internal DPLL support 26-20 MPC8260 PowerQUICC II UserÕs Manual is issued, one break STOP TRANSMIT COMMAND MOTOROLA...

  • Page 717: Features

    For instance, if a single TxBD is initialized with the CM and W bits set, the buffer is sent continuously until R is cleared in the BD. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module...

  • Page 718: Smc Transparent Channel Reception Process

    Glitches on SMSYN can cause errant behavior of the SMC. The transmitter never loses synchronization again, regardless of the state of SMSYN, until the TEN bit is cleared or an command is issued. ENTER HUNT MODE 26-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 719: Using The Time-Slot Assigner (Tsa) For Synchronization

    The TSA allows the SMC receiver and transmitter to be enabled simultaneously and synchronized separately; SMSYN does not provide this capability. Figure 26-12 shows synchronization using the TSA. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module...
  • Page 720 SMC time slot, but not necessarily the Þrst time slot after the frame sync. So, to maintain a certain bit alignment beginning with the Þrst time slot, make sure that at least one TxBD is 26-24 MPC8260 PowerQUICC II UserÕs Manual SMC1 the beginning of either time slot.

  • Page 721: Smc Transparent Commands

    Then the channel closes the buffer, sets OV in the BD, and generates the RXB interrupt if it is enabled. Reception continues as normal. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module Description command resets transmit and receive parameters.

  • Page 722: Smc Transparent Rxbd

    Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received data is placed into the buffer. Ñ Reserved, should be cleared. 26-26 MPC8260 PowerQUICC II UserÕs Manual command is issued. Ñ Data Length Rx Data Buffer Pointer Description Ñ...

  • Page 723: Smc Transparent Txbd

    Ñ Reserved, should be cleared. Underrun. Set when the SMC encounters a transmitter underrun condition while sending the buffer. Ñ Reserved, should be cleared. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module Ñ Data Length Tx Data Buffer Pointer Description Ñ...

  • Page 724: Smc Transparent Event Register (Smce)/Mask Register (Smcm)

    FIFO. A two character-time delay is required to ensure that data is completely sent. Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and its associated RxBD is now closed. 26-28 MPC8260 PowerQUICC II UserÕs Manual Ñ Description ENTER HUNT MODE...

  • Page 725: Smc Transparent Nmsi Programming Example

    After 5 bytes are sent, the TxBD is closed; after 16 bytes are received the receive buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module...

  • Page 726: The Smc In Gci Mode

    From the pointer value programmed in SMCx_BASE: SMC1_BASE at 0x87FC, SMC2_BASE at 0x88FC. RSTATE, M_RxD, M_TxD, CI_RxD, and CI_TxD do not need to be accessed by the user in normal operation, and are reserved for RISC use only. 26-30 MPC8260 PowerQUICC II UserÕs Manual Description Rx/Tx Internal State MOTOROLA...

  • Page 727: Handling The Gci Monitor Channel

    The SMC receives data and handles the A and E control bits according to the GCI monitor channel protocol. When the CP stores a received data byte in the SMC RxBD, a maskable interrupt is generated. A command causes the MPC8260 to TRANSMIT ABORT REQUEST send an abort request on the E bit.

  • Page 728: Smc Gci Commands

    It is usually issued because the device is not responding or A bit errors are detected. The MPC8260 sends an abort request on the E bit at the time this command is issued. 26.5.5 SMC GCI Monitor Channel RxBD This BD is used by the CP to report information about the monitor channel receive byte.

  • Page 729: Smc Gci C/I Channel Rxbd

    26.5.8 SMC GCI C/I Channel TxBD The CP uses this BD to report about the C/I channel transmit byte. Offset + 0 Figure 26-18. SMC C/I Channel TxBD MOTOROLA Chapter 26. Serial Management Controllers (SMCs) Part IV. Communications Processor Module Description Ñ...

  • Page 730: Smc Gci Event Register (Smce)/Mask Register (Smcm)

    C/I channel buffer received. Set when the C/I receive buffer is full. MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer is now empty. MRXB Monitor channel buffer received. Set when the monitor receive buffer is full. 26-34 MPC8260 PowerQUICC II UserÕs Manual Description CTXB CRXB 0000_0000 Description...

  • Page 731: Multi-Channel Controllers (Mccs)

    Chapter 27 Multi-Channel Controllers (MCCs) The MPC8260Õs two multi-channel controllers (MCC1 and MCC2) each handle up to 128 serial, full-duplex data channels. The 128 channels are divided into four subgroups (of 32 channels each). One or more subgroups can be multiplexed through corresponding SIx TDM channels;...

  • Page 732: Mcc Data Structure Organization

    (base address RINTBASE0ÐRINTBASE4). TINTBASE and RINTBASE0ÐRINTBASE4 are global MCC parameters. ¥ Three registers (MCCE, MCCM, and MCCF) at described in Section 27.10.1, ÒMCC Event Register (MCCE)/Mask Register (MCCM),Ó and Section 27.8, ÒMCC ConÞguration Registers (MCCFx).Ó 27-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 733: Global Mcc Parameters

    GRFCNT each time a frame is received. When GRFCNT underßows the CP generates an interrupt and copy GRFTHR to GRFCNT. This parameter does not need to be reset after an interrupt. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module...
  • Page 734 RINTBASEx value to RINTPTRx before enabling interrupts. Further updates of the RINTPTRx are done by the CP. 0x50 RINTBASE2 Word 0x54 RINTPTR2 Word 0x58 RINTBASE3 Word 0x5C RINTPTR3 Word 0x60 TS_TMP Word Temporary place for time stamp Offset to MCC Base 27-4 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 735: Channel Extra Parameters

    1, 6, and 7 and the second 2, 3, and 4. Figure 27-4 shows the SI RAM programming for the same transparent receiver super MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module...
  • Page 736 The super channel BD tables are associated with channels 1 and 2 (no BD tables are necessary for channels 3, 4, 6, and 7) Figure 27-3. Transmitter Super Channel Example The example in Figure 27-5 shows a receiver super channel with slot synchronization. 27-6 MPC8260 PowerQUICC II UserÕs Manual 11Ð13 0Ð1 DPR_Base + SCTPBASE + 0x10 Super Channel Table 2Ð9...
  • Page 737 The example in Figure 27-5 shows a receiver super channel without slot synchronization. LOOP SUPER The super channel BD tables are associated with channels 1 and 2 Figure 27-5. Receiver Super Channel without Slot Synchronization Example MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module SI RAM 3Ð10...
  • Page 738 MAX_CNT Hword Max_length counter, used by the CP (read-only for the user) 0x3C RCRC Word Temp receive CRC, used by the CP (read-only for the user) The offset is relative to dual-port RAM base address + 64*CH_NUM 27-8 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 739: Internal Transmitter State (Tstate)

    1 Local bus SDMA used for accessing BDs 27.6.2 Interrupt Mask (INTMSK) The interrupt mask (INTMSK) provides in bits for enabling/disabling each event deÞned in the interrupt circular table entry. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module Ñ...

  • Page 740: Channel Mode Register (Chamr)

    To minimize useless transactions on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R] before enabling polling. Must be set. 27-10 MPC8260 PowerQUICC II UserÕs Manual Ñ Mask Bits Ñ...

  • Page 741: Internal Receiver State (Rstate)

    RSTATE high byte (see Figure 27-9). When the channel is active the CP changes the value of the 3 LSBs, hence these 3 bytes must be masked if the user reads back the RSTATE. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV.
  • Page 742 Word Tx internal state. To start a transmitter channel the user must write to TSTATE 0xHH80_0000. HH is the TSTATE high byte described in Section 27.6.1, ÒInternal Transmitter State (TSTATE).Ó 27-12 MPC8260 PowerQUICC II UserÕs Manual Ñ 0x20 Description Description...

  • Page 743: Channel Mode Register (Chamr)Ñtransparent Mode

    The offset is relative to dual-port RAM address 64*CH_NUM 27.7.1 Channel Mode Register (CHAMR)ÑTransparent Mode Figure 27-10 shows the user-initialized channel mode register, CHAMR, for transparent mode. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module Description 27-13...
  • Page 744 8-bit None 16-bit None 8Ð9 Ñ Reserved, must be cleared. 27-14 MPC8260 PowerQUICC II UserÕs Manual SYNC Ñ Ñ 0x1A Description Description Transmitter and receiver operate with no synchronization algorithm The Þrst data is sent/received in the slot deÞned in the slot assignment table (for super channels only) Receive data synchronization uses an 8-bit pattern speciÞed by the 8...
  • Page 745 Name 0Ð1, 2Ð3, 4Ð5, 6Ð7 GROUP x Group x of channels is used by TDM y as shown in Table 27-10. Table 27-10 describes group assignments. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module Description Group 2...

  • Page 746: Mcc Commands

    32 consecutive channels starting with the channel number speciÞed in CPCR[MCN]. To initialize more than 32 channels, reissue the command with the appropriate channel numbers. Note also the TX AND RX PARAMETERS 27-16 MPC8260 PowerQUICC II UserÕs Manual Group Channels 0Ð31 32Ð63...

  • Page 747: Mcc Exceptions

    CP. All the entries in the table must be user-initialized with 0x00000000, except for the last one which must be initialized with 0x40000000 (W = 1, thus deÞning the MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module Description 2Ð17...

  • Page 748: Mcc Event Register (Mcce)/Mask Register (Mccm)

    QOV0 RINT0 QOV1 RINT1 QOV2 RINT2 QOV3 RINT3 Reset Addr 0x11B30 (MCCE1), 0x11B50 (MCCE2)/0x11B34 (MCCM1), 0x11B54 (MCCM2) Figure 27-13. MCC Event Register (MCCE)/Mask Register (MCCM) 27-18 0000_0000_0000_0000 MPC8260 PowerQUICC II UserÕs Manual 9 10 11 Ñ TQOV TINT GUN GOV MOTOROLA...

  • Page 749: Interrupt Table Entry

    Each interrupt table entry, shown in Figure 27-14, contains information about channel- speciÞc events. The transmit circular table shows only events caused by transmission; the receive circular tables shows only events caused by reception. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module...
  • Page 750 RxBD. 16Ð18 Ñ Reserved, should be cleared. 19Ð26 CN Channel number. IdentiÞes the requests channel index (0Ð255). 27Ð31 Ñ Reserved, should be cleared. 27-20 MPC8260 PowerQUICC II UserÕs Manual Ñ Channel Number Description MRF RXF BSY RXB MOTOROLA...

  • Page 751: Mcc Buffer Descriptors

    CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame octets to the data length Þeld. 0 This buffer is not the last in a frame. 1 This buffer is the last in a frame. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module Ñ...
  • Page 752 Rx CRC error. This frame contains a CRC error. The received CRC bytes are always written to the receive buffer. 14Ð15 Ñ Reserved, should be cleared. 27-22 MPC8260 PowerQUICC II UserÕs Manual Description xxx ... xx Valid data Invalid data 000...

  • Page 753: Transmit Buffer Descriptor (Txbd)

    (if enabled). Last 0 This is not the last buffer in the frame. 1 This is the last buffer in the current frame. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module Ñ...

  • Page 754: Mcc Initialization And Start/Stop Sequence

    The MCC must be initialized and started/stopped in relation with the corresponding TDMs. The following two sections present the initialization and start/stop sequences which must be followed for single and super channels. 27-24 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 755: Single-Channel Initialization

    3. Enable the MCC channel(s) as described in Section 27.6.1, ÒInternal Transmitter State (TSTATE),Ó and Section 27.6.4, ÒInternal Receiver State (RSTATE),Ó or change the associated SI RAM entry to point to the respective channel. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) Part IV. Communications Processor Module...

  • Page 756: Super Channel Initialization

    If no super channels are active, the MCC can handle aggregate data rates of up to 16 Mbps on each of the four channel subgroups. If super channels are used this performance is limited to 8 Mbps. 27-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 757 This avoids bus activity peaks when all the channels have to transfer data to/from the memory simultaneously. MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-27...
  • Page 758 Part IV. Communications Processor Module 27-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 759: Fast Communications Controllers (Fccs)

    Chapter 28 Fast Communications Controllers (FCCs) The MPC8260Õs fast communications controllers (FCCs) are serial communications controllers (SCCs) optimized for synchronous high-rate protocols. FCC key features include the following: ¥ Supports HDLC/SDLC and totally transparent protocols ¥ FCC clocks can be derived from a baud-rate generator or an external signal.

  • Page 760: Overview

    FCC can be connected to its own set of pins on the MPC8260. This conÞguration, the nonmultiplexed serial interface, or NMSI, is described in Chapter 14, ÒSerial Interface with Time-Slot Assigner.Ó In this conÞguration, each FCC can support the standard modem interface signals (RTS, CTS, and CD) through the appropriate port pins and the interrupt controller.

  • Page 761: General Fcc Mode Registers (Gfmrx)

    Bits Field SYNL RTSM RENC Reset Addr 0x11302 (GFMR1), 0x11322 (GFMR2), 0x11342 (GFMR3) Figure 28-2. General FCC Mode Register (GFMR) MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) Part IV. Communications Processor Module 60x Bus Control Registers Peripheral Bus Receive Transmit...
  • Page 762 0 Normal operation. 1 The FCC inverts the internal transmit clock. Transparent receiver. The MPC8260 FCCs offer totally transparent operation. However, to increase ßexibility, totally transparent operation is conÞgured with the TTX and TRX bits instead of the MODE bits. This lets the user implement unique applications such as an FCC transmitter conÞgured to HDLC and a receiver conÞgured to totally transparent operation.
  • Page 763 CTS must transition while the transmit clock is in the low state. As soon as CTS is low, data transmission begins. This mode is useful when connecting MPC8260 in transparent mode because it allows the RTS signal of one MPC8260 to be connected directly to the CTS signal of another MPC8260.
  • Page 764 0111 Reserved for RAM microcode 1000 Reserved 1001 Reserved for RAM microcode 1010 ATM 1011 Reserved for RAM microcode 1100 Ethernet 11xx Reserved 28-6 MPC8260 PowerQUICC II UserÕs Manual Description command, and RxBD[E]. CLOSE RXBD , and commands, CTS ßow control, RESTART TRANSMIT MOTOROLA...

  • Page 765: Fcc Data Synchronization Registers (Fdsrx)

    If a new TxBD is added to the BD table while preceding TxBDs have not completed transmission, the new TxBD is processed immediately after the older TxBDs are sent. MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) Part IV. Communications Processor Module...

  • Page 766: Fcc Buffer Descriptors

    (BD) that can be anywhere in external memory. The BD table forms a circular queue with a programmable length. The user can program the start address of each channel BD table anywhere in memory. See Figure 28-3. 28-8 MPC8260 PowerQUICC II UserÕs Manual Ñ 0000_0000_0000_0000 Description...
  • Page 767 BD table must always contain at least one empty BD to avoid a busy error; therefore, RxBD tables must always have at least two BDs. MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) Part IV. Communications Processor Module...

  • Page 768: Fcc Parameter Ram

    Each FCC parameter RAM area begins at the same offset from each FCC base area. The protocol-speciÞc portions of the FCC parameter RAM are discussed in the speciÞc protocol descriptions. Table 28-5 shows portions common to all FCC protocols. 28-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 769: Normal Operation

    Word Receive internal state. The high byte, RSTATE[0Ð7], contains the function code register; see Section 28.7.1, ÒFCC Function Code Registers (FCRx).Ó RSTATE[8Ð31] is used by the CP and must be cleared initially. MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) Part IV. Communications Processor Module...
  • Page 770 0x38 First word of protocol-speciÞc area Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 13.5.2, ÒParameter RAM.Ó 28-12 MPC8260 PowerQUICC II UserÕs Manual Description command is issued and the frame completes transmission). STOP TRANSMIT GRACEFUL STOP...

  • Page 771: Fcc Function Code Registers (Fcrx)

    LSB of the buffer double-word contains data to be sent earlier than the MSB of the same buffer double-word. 10 Motorola byte ordering (normal operation). It is also called big-endian byte ordering. As data is sent onto the serial line from the data buffer, the MSB of the buffer word contains data to be sent earlier than the LSB of the same buffer word.

  • Page 772: Fcc Event Registers (Fccex)

    3. If the TSA is used, the SI must be conÞgured. If the FCC is used in the NMSI mode, the CPM multiplexing logic (CMX) must still be initialized. 4. Write the GFMR, but do not write the ENT or ENR bits yet. 5. Write the FPSMR. 28-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 773: Fcc Interrupt Handling

    When GFMR[DIAG] is programmed to normal operation, CD and CTS are automatically controlled by the FCC. GFMR[TCI] is assumed to be cleared, which implies normal transmit clock operation. MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) Part IV. Communications Processor Module command (with the correct protocol number).
  • Page 774 CTS is asserted. Figure shows that the delay between CTS and the data can be approximately 0.5- to 1-bit time in asynchronous mode (if GFMR[CTSS] = 0) or 0 bit times (if GFMR[CTSS] = 1). 28-16 MPC8260 PowerQUICC II UserÕs Manual Last Bit of Frame Data MOTOROLA...
  • Page 775 If GFMR[CTSS] = 0, the FCC must sample CTS before a CTS lost is recognized. Otherwise, the negation of CTS immediately causes the CTS lost condition. See Figure 28-8. MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) Part IV. Communications Processor Module...
  • Page 776 If GFMR[CDS] = 1, CD transitions immediately cause data to be gated into the receiver. 28-18 MPC8260 PowerQUICC II UserÕs Manual First Bit of Frame Data CTS Sampled High First Bit of Frame Data Figure 28-8.

  • Page 777: Disabling The Fccs On-The-Fly

    Modifying parameter RAM does not require the FCC to be fully disabled. See the parameter RAM description for when values can be changed. To disable all peripheral controllers, set CPCR[RST] to reset the entire CPM. MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) Part IV. Communications Processor Module...

  • Page 778: Fcc Transmitter Full Sequence

    4. Set GFMR[ENR]. Reception begins immediately using the RxBD that the RBPTR points to if RxBD[E] = 1. 28-20 MPC8260 PowerQUICC II UserÕs Manual command. This is recommended if the FCC is currently GRACEFUL STOP TRANSMIT command is not required.

  • Page 779: Fcc Receiver Shortcut Sequence

    3. Set GFMR[ENT] and GFMR[ENR]. The FCC is enabled with the new protocol. 28.13 Saving Power Clearing an FCCÕs ENT and ENR bits minimizes its power consumption. MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) Part IV. Communications Processor Module command. Any additional changes can be made now.
  • Page 780 Part IV. Communications Processor Module 28-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 781: Atm Controller

    Þrmware (without software intervention) to prevent potential delays during backward RM cell processing and feedback rate adaptation. The MPC8260 supports a special mode for ATM/TDM interworking. The CPM performs automatic data forwarding between ATM channels and the MCCsÕ TDM channels without core intervention.

  • Page 782: Features

    Ð Automatic CPCS_UU, CPI, and length insertion Ð Abort message option ¥ AAL1 cell format Ñ Reassembly Ð Reassemble PDU directly to external memory Ð Support for partially Þlled cells (conÞgurable on a per-VC basis) MOTOROLA Part IV. Communications Processor Module Chapter 29. ATM Controller 29-2...
  • Page 783 Ñ Peak-and-sustain cell rate pacing using GCRA on a per-VC basis Ñ Peak-and-minimum cell rate pacing on a per-VC basis Ñ Up to eight priority levels Ñ Fully managed by CP with no host intervention 29-3 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 784: Atm Controller Overview

    Ñ RxBD table per VC with option of global free buffer pool for AAL5 Ñ TxBD table per VC 29.2 ATM Controller Overview The following sections provide an overview of the transmitter and receiver portions of the ATM controller. MOTOROLA Part IV. Communications Processor Module count count ) generation/check...

  • Page 785: Transmitter Overview

    Part IV. Communications Processor Module 29.2.1 Transmitter Overview Before the transmitter is enabled, the host must initialize the MPC8260 and create the transmit data structure, described in Section 29.10, ÒATM Memory Structure.Ó When data is ready for transmission, the host arranges the BD table and writes the pointer of the Þrst BD in the transmit connection table (TCT).

  • Page 786: Aal0 Transmitter Overview

    29.2.2 Receiver Overview Before the receiver is enabled, the host must initialize the MPC8260 and create the receive data structure described in Section 29.10, ÒATM Memory Structure.Ó The host arranges a BD table for each ATM channel. Buffers for each connection can be statically allocated (that is, each BD in the BD table is associated with a Þxed buffer location) or in the case of...

  • Page 787: Aal5 Receiver Overview

    (SNP) (CRC-3 and parity bit), is checked. The MPC8260 supports SRTS clock recovery using an external PLL. In this mode, the MPC8260 tracks the SRTS from the four incoming cells and writes the SRTS code to external logic. See Section 29.15, ÒSRTS Generation and Clock Recovery Using External Logic.Ó...

  • Page 788: Aal0 Receiver Overview

    The MPC8260 supports partially Þlled cells conÞgured on a per-VC basis. In this mode, the ATM controller copies only the valid octets from the cell user data Þeld to the buffer.

  • Page 789: Apc Unit Scheduling Mechanism

    (speciÞed in time slots). The PCR parameter in the TCT, or the SCR or MCR parameters in the TCT extension (TCTE) determine the channelÕs actual rate. 29-9 MPC8260 PowerQUICC II UserÕs Manual Real-Time/ Cell Rate Pacing Non-Real-Time...

  • Page 790: Determining The Scheduling Table Size

    CPS increases, the CDV increases. However as CPS decreases, the size of the scheduling table in the dual-port RAM increases and more CPM bandwidth is required. 29-10 MPC8260 PowerQUICC II UserÕs Manual Number of Slots Cell Rescheduling line rate...

  • Page 791: Determining The Number Of Slots In A Scheduling Table

    Suppose a VC uses 15.66 Mbps of the total 155.52 Mbps and CPS = 8. Equation C yields: PCR [slots] = (155.52 Mbps)/(15.66 Mbps ´ 8) = 1.241 29-11 MPC8260 PowerQUICC II UserÕs Manual line rate (number_of_slots - 1) ´ cells per slot line rate [bps] VC rate [bps] ´...
  • Page 792 Equation C (see Section 29.3.4, ÒDetermining the Time-Slot Scheduling Rate of a ChannelÓ) yields the APC SCR_FRACTION, which the user writes to the channelÕs TCT. 29-12 MPC8260 PowerQUICC II UserÕs Manual PCR_FRACTION = 62 Conforming VBR Traffic Sustained cell rate (SCR) parameters, PCR,...

  • Page 793: Handling The Cell Loss Priority (Clp)Ñvbr Type 1 And 2

    BT [slots] = (MBS[cells] - 2) ´ (SCR[slots] - PCR[slots]) + SCR[slots] 29.3.5.3.2 Handling the Cell Loss Priority (CLP)ÑVBR Type 1 and 2 The MPC8260 supports two ways to schedule VBR trafÞc based on the cell loss priority (CLP). When TCTE[VBR2] is cleared, CLP according to the GCRA state.

  • Page 794: Vci/Vpi Address Lookup Mechanism

    Part IV. Communications Processor Module 29.4 VCI/VPI Address Lookup Mechanism The MPC8260 supports two ways to look up addresses for incoming cells: ¥ External CAM lookup ¥ Address compression Writing to GMODE[ALM] (address-lookup-mechanism bit) in the parameter RAM selects the mechanism. Both mechanisms are described in the following sections.

  • Page 795: Address Compression

    In the VC-level translation, the VCI is compressed with the VC_MASK to generate a pointer to the VC-level table entry containing the received cellÕs channel code. The VC table should reside in external memory. Figure 29-5 shows an example of address compression. 29-15 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...
  • Page 796 Ch Code Pointer to internal or external connection table. Ñ Reserved, should be cleared. Match status. 0 Match was found. 1 Match was not found. 29-16 MPC8260 PowerQUICC II UserÕs Manual VP-level addressing table (in dual-port RAM recommended) VPT_BASE VP_MASK 32-bit entries VCT_BASE...

  • Page 797: Vp-Level Address Compression Table (Vplt)

    0x0237 0x0230 0xA007 The MPC8260 can check that all unallocated bits of the PHY + VPI are 0 by setting GMODE[CUAB] (check unallocated bits) in the parameter RAM. If they are not, the cell is considered a misinserted cell. Table 29-5 gives an example of VP-level table entry address calculation.

  • Page 798: Vc-Level Address Compression Tables (Vclts)

    0b11_1111_1111, the table is 4 Kbytes. The address of an entry in this table is VCT_BASE + VCOFFSET ´ 4 + VCpointer ´ 4. The MPC8260 can check that all unallocated VCI bits are 0 by setting GMODE[CUAB] (check unallocated bits). If they are not, the cell is considered a misinserted cell.

  • Page 799: Receive Raw Cell Queue

    Figure 29-9. ATM Address Recognition Flowchart Note that even reserved VCI channels should appear in the CAM or address compression tables; otherwise, a cell on a reserved channel will be considered misinserted. 29-19 MPC8260 PowerQUICC II UserÕs Manual Check address Match...

  • Page 800: Available Bit Rate (Abr) Flow Control

    ABR service is intended for data applications that can adapt to time-varying bandwidth and can tolerate signiÞcant cell transfer delay and cell delay variation. The MPC8260 implements the two following mechanisms deÞned by the ATM Forum TM 4.0 rate-based ßow control.

  • Page 801: Abr Flow Control Source End-System Behavior

    Part IV. Communications Processor Module The MPC8260 ABR ßow control implements both source and destination behavior. The MPC8260Õs ABR ßowchart is described in Section 29.5.1.3, ÒABR Flowcharts.Ó 29.5.1.1 ABR Flow Control Source End-System Behavior The MPC8260Õs implementation of ABR ßow control for end-system sources is described in the following steps: 1.

  • Page 802: Abr Flowcharts

    RM cell overwrites the old RM cell. 29.5.1.3 ABR Flowcharts The MPC8260Õs ABR transmit and receive flow control is described in the following ßowcharts. See Figure 29-11, Figure 29-12, Figure 29-13, and Figure 29-14. Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = 0, CLP =1) Schedule: Time_to_send = now+1/TCR Figure 29-11.
  • Page 803 Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = CLP = 0) Figure 29-12. ABR Transmit Flow (Continued) 29-23 MPC8260 PowerQUICC II UserÕs Manual RM/DATA In Rate Cell Tx Count=Number of data cells from last F-RM.
  • Page 804 Part IV. Communications Processor Module Send RM cell (DIR = backwards, CCR-TA, ER-TA, MCR-TA, Figure 29-13. ABR Transmit Flow (Continued) 29-24 MPC8260 PowerQUICC II UserÕs Manual B-RM/DATA In Rate Cell Tx Turn-around (First-turn or not data-in-queue) Destination End-Sys 1,2,3,4 B-RM In Rate Cell Tx...

  • Page 805: Rm Cell Structure

    Figure 29-14. ABR Receive Flow 29.5.2 RM Cell Structure Table 29-7 describes the structure of the RM cell supported by the MPC8260. For more information, see the ABR ßow-control trafÞc management speciÞcation (TM 4.0) on the ATM Forum website at http://www.atmforum.com.

  • Page 806: Rm Cell Rate Representation

    The rate (in cells/second) is calculated as in Figure 29-16. Figure 29-16. Rate Formula for RM Cells Initialize the trafÞc parameters (ER, MCR, PCR, or ICR) in the ABR protocol-speciÞc connection tables using the rate formula in Figure 29-16. 29-26 MPC8260 PowerQUICC II UserÕs Manual Description Mantissa æ ö...

  • Page 807: Abr Flow Control Setup

    ATM TRANSMIT 29.6 OAM Support This section describes the MPC8260Õs support for ATM-layer (F4 out-of-band, and F5 in- band) operations and maintenance (OAM) of connections. Alarm surveillance, continuity checking, remote defect indication, and loopback cells are supported using OAM receive and transmit AAL0 cell queues.

  • Page 808: Virtual Path (F4) Flow Mechanism

    OAM F4/F5 ßow cells are received using the raw cell queue, described in Section 29.4.4, ÒReceive Raw Cell Queue.Ó An F4/F5 OAM cell which does not appear in the CAM or address compression tables is considered a misinserted cell. 29-28 MPC8260 PowerQUICC II UserÕs Manual aaaa_aaaa_aaaa 0000_0000_0000_0011 aaaa_aaaa_aaaa...

  • Page 809: Transmitting Oam F4 Or F5 Cells

    (BRC), which is then returned to the opposite endpoint. The MPC8260 can run up to 64 bidirectional block tests simultaneously. When a bidirectional test is run, FMCs are generated for one direction and checked for the opposite.

  • Page 810: Running A Performance Block Test

    29.6.6.2 PM Block Monitoring PM block monitoring is done by the receiver. After initialization (see Section 29.6.6.1), whenever a cell is received for a VCC or VPC, the TRCC counters are incremented and the 29-30 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 811: Pm Block Generation

    , BEDC from the performance monitoring table and inserts them into the FMC payload. The TSTP value (FMC time stamp Þeld) is taken from the MPC8260 time stamp timer; see Section 13.3.7, ÒRISC Time-Stamp Control Register (RTSCR).Ó The TUCs are free-running counters (modulo 65,536) that count transmitted user cells. The total transmitted cells of a particular block is the difference between TUC values of two consecutive FMCs.

  • Page 812: Brc Performance Calculations

    Typical ATM cells are 53 bytes long and consist of a 4-byte header, 1-byte HEC, and 48- byte payload. The MPC8260 also supports user-deÞned cells with up to 12 bytes of extra header Þelds for internal information for switching applications. This choice is made during initialization by writing to the FPSMR;...

  • Page 813: Udc Extended Address Mode (Uead)

    ¥ Misinserted dropped cell countÑCounts cells discarded due to address look-up failure. ¥ CRC10 error dropped cell countÑCounts cells discarded due to CRC10 errors. (ABR only). 29-33 MPC8260 PowerQUICC II UserÕs Manual Extra Header (1Ð12 Bytes) Payload (48 Bytes) 4-bit 12-bit...

  • Page 814: Atm-To-Tdm Interworking

    Statistics Table.Ó 29.9 ATM-to-TDM Interworking The MPC8260 supports ATM and TDM interworking. The MCCs and their corresponding SIs handle the TDM data processing. (See Chapter 27, ÒMulti-Channel Controllers (MCCs),Ó and Chapter 14, ÒSerial Interface with Time-Slot Assigner.Ó) The ATM controller processes the ATM data.

  • Page 815: Using Interrupts In Automatic Data Forwarding

    For example, to start the MCC transmitter after a speciÞc buffer reaches the ATM receiver (the buffering is required to 29-35 MPC8260 PowerQUICC II UserÕs Manual BD Table BD 1 MCC Tx ptr...

  • Page 816: Timing Issues

    The SRTS method may be implemented using external logic. The MPC8260 can read the SRTS from external logic and insert it into AAL1 cells, and can track the SRTS from AAL1 cells and deliver it to external logic. See Section 29.15, ÒSRTS Generation and Clock Recovery Using External Logic.Ó...

  • Page 817: Trunk Condition

    RAM, the connection tables, OAM performance monitoring tables, the APC data structure, BD tables, the AAL1 sequence number protection table and the UNI statistics table. 29.10.1 Parameter RAM When conÞgured for ATM mode, the FCC parameter RAM is mapped as shown in Table 29-11. 29-37 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 818 0x6A UNI_STATT_BASE Hword UNI statistics table base. User-deÞned offset from dual-port RAM base. 29-38 MPC8260 PowerQUICC II UserÕs Manual Description Reserved, should be cleared. port RAM area used by the CP. Should be 64 byte aligned. User-deÞned offset from dual-port RAM base. (Recommended address space: 0x3000-0x4000 or 0xB000Ð0xC000)
  • Page 819 EPAYLOAD Word 0xA8 Word 29-39 MPC8260 PowerQUICC II UserÕs Manual Description BD table base address extension. BD_BASE_EXT[0Ð7] holds the 8 most- signiÞcant bits of the Rx/Tx BD table base address. BD_BASE_EXT[8Ð31] should be zero. User-deÞned. Base address of the address compression VP table/external CAM. User- deÞned.

  • Page 820: Determining Uead_Offset (Uead Mode Only)

    0 Do not send cells with this VCI to the raw cell queue. 1 Send cells with this VCI to the raw cell queue. 29-40 MPC8260 PowerQUICC II UserÕs Manual Description cell. Set to 32 cells. Set to 2 cells.

  • Page 821: Global Mode Entry (Gmode)

    These include AAL type, connection trafÞc parameters, BD parameters and temporary parameters used during segmentation and reassembly (SAR). The transmit connection table extension (TCTE) supports special connections that 29-41 MPC8260 PowerQUICC II UserÕs Manual ALB CTB REM Description UEAD CUAB EVPT...

  • Page 822: Atm Channel Code

    (64 VCs ´ 64 bytes (RCT and TCT) = 4 K). Channels 0Ð1 are reserved. The remaining 962 (1024 - 62) external channels are assigned channel codes 256Ð1217. See Figure 29-24. 29-42 MPC8260 PowerQUICC II UserÕs Manual 32 bytes 32 bytes 32 bytes...

  • Page 823: Receive Connection Table (Rct)

    See Section 29.10.1, ÒParameter RAM,Ó to Þnd all the connection table base address parameters. (The transmit connections table base address parameters are INT_TCT_BASE, EXT_TCT_BASE, INT_TCTE_BASE, and EXT_TCTE_BASE.) 29.10.2.2 Receive Connection Table (RCT) Figure 29-25 shows the format of an RCT entry. 29-43 MPC8260 PowerQUICC II UserÕs Manual EXT_RCT_BASE Reserved RCT2 RCT3 RCT63...
  • Page 824 Offset + 0x18 Offset + 0x1A Offset + 0x1C Ñ Offset + 0x1E Figure 29-25. Receive Connection Table (RCT) Entry 29-44 MPC8260 PowerQUICC II UserÕs Manual Ñ DTB Ñ BUFM SEGF ENDF Ñ RX Data Buffer Pointer (RXDBPTR) Cell Time Stamp RBD_Offset Protocol SpeciÞc...
  • Page 825 0 ABR ßow control is disabled. 1 ABR ßow control is enabled. 13Ð15 AAL type 000 AAL0ÑReassembly with no adaptation layer 001 AAL1ÑATM adaptation layer 1 protocol 010 AAL5ÑATM adaptation layer 5 protocol All others reserved. 29-45 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 826: Aal5 Protocol-Specific Rct

    Receive data buffer pointer. Holds real address of current position in the Rx buffer. 0x08 Ñ Cell Time Used for reassembly time-out. Whenever a cell is received, the MPC8260 time stamp Stamp timer is sampled and written to this Þeld. See Section 13.3.7, ÒRISC Time-Stamp Control Register (RTSCR).Ó...

  • Page 827: Aal5-Abr Protocol-Specific Rct

    Figure 29-27 shows the AAL5-ABR protocol-speciÞc area of an RCT entry. Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Figure 29-27. AAL5-ABR Protocol-Specific RCT 29-47 MPC8260 PowerQUICC II UserÕs Manual Description AAL5 Protocol-SpeciÞc AAL5 Protocol-SpeciÞc MOTOROLA...

  • Page 828: Aal1 Protocol-Specific Rct

    Offset + 0x18 Ñ Figure 29-28. AAL1 Protocol-Specific RCT Table 29-19 describes AAL1 protocol-speciÞc RCT Þelds. 29-48 MPC8260 PowerQUICC II UserÕs Manual Description -RDF . The decrease factor ranges from 1/32768 (RDF=0xF) to 1 (RDF=0). -RIF . The increase factor ranges from 1/32768 (RIF=0xF) to 1 (RIF=0).
  • Page 829 Synchronous residual time stamp. Unstructured format only. The MPC8260 supports clock recovery using an external SRTS PLL. The MPC8260 tracks the SRTS from the incoming four cells with SN = 1, 3, 5, and 7 and writes it to the external SRTS device.

  • Page 830: Aal0 Protocol-Specific Rct

    1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty). 11-15 Ñ Reserved, should be cleared. 0x10 Ñ Ñ Reserved, should be cleared. 29-50 MPC8260 PowerQUICC II UserÕs Manual Description Ñ Ñ Ñ RXBM Description INVE Ñ...

  • Page 831: Transmit Connection Table (Tct)

    Offset + 0x1a Offset + 0x1C Ñ Offset + 0x1E Figure 29-30. Transmit Connection Table (TCT) Entry Table 29-21 describes general TCT Þelds. 29-51 MPC8260 PowerQUICC II UserÕs Manual Description Ñ DTB BIB AVCF Ñ Ñ Tx Data Buffer Pointer (TXDBPTR)
  • Page 832 APC scheduling table. The host can issue another 14Ð15 INTQ Points to one of four interrupt queues available. 29-52 MPC8260 PowerQUICC II UserÕs Manual Description ATM TRANSMIT command only after the CP clears VCON. ATM TRANSMIT command is needed, ATM TRANSMIT command.
  • Page 833 TCT[VCON] when the channel is next encountered in the APC scheduling table. Note that for AAL5 if STPT is set and frame transmission is already started (TCT[INF]=1), an abort indication will be sent (last cell with zero length Þeld). 29-53 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 834: Aal5 Protocol-Specific Tct

    Valid Octet Size (VOS) Offset + 0x12 SRTS Device Offset + 0x14 SRTS_TMP Figure 29-32. AAL1 Protocol-Specific TCT 29-54 MPC8260 PowerQUICC II UserÕs Manual Description Tx CRC Total Message Length Description CRC32 temporary result. This Þeld is used by the CP.

  • Page 835: Aal0 Protocol-Specific Tct

    Synchronous residual time stamp. Unstructured format only. The MPC8260 supports SRTS generation using external logic. If this mode is enabled, the MPC8260 reads the SRTS from external logic and inserts it into four cells for which SN = 1, 3, 5, or 7. The MPC8260 reads the new SRTS from external logic every eight cells.
  • Page 836 OOBR Out-of-buffer rate. In out of buffer state (when the transmitter tries to open TxBD whose R bit is not set) the APC reschedules the current channel according to OOBR rate. 29-56 MPC8260 PowerQUICC II UserÕs Manual Description Burst Tolerance (BT)

  • Page 837: Ubr+ Protocol-Specific Tcte

    Maximum delay allowed. The maximum time-slot service delay allowed for this priority level before the APC reduces the scheduling rate from PCR to MCR. 0x06Ð Ñ Ñ Reserved, should be cleared. 0x1E 29-57 MPC8260 PowerQUICC II UserÕs Manual Description Ñ Maximum Delay Allowed (MDA) Ñ Description MCR Fraction (MCRF) MOTOROLA...

  • Page 838: Abr Protocol-Specific Tcte

    No increaseÐturn-around cell. Holds the NI of the last received F-RM cell. If another F-RM cell arrives before the previous one was turned around, NI-TA is overwritten by the new RM cellÕs NI. 29-58 MPC8260 PowerQUICC II UserÕs Manual ER-TA CCR-TA MCR-TA Ñ...
  • Page 839 B-RM cells. The ER-TA Þeld which is inserted to each B-RM cell is limited by this value. ER-BRM uses the ATMF TM 4.0 ßoating-point format. 29-59 MPC8260 PowerQUICC II UserÕs Manual Description . The cutoff decrease factor ranges from 1/64 (CDF=0b0110) to 1...

  • Page 840: Oam Performance Monitoring Tables

    Offset + 0x18 Offset + 0x1A Offset + 0x1C Offset + 0x1E Figure 29-37. OAM Performance Monitoring Table Table 29-28 describes Þelds in the performance monitoring table. 29-60 MPC8260 PowerQUICC II UserÕs Manual Ñ TX Cell Count (TCC) TUC1 TUC0 BEDC0+1-Tx BEDC0+1-RX...

  • Page 841: Apc Data Structure

    29.10.4 APC Data Structure The APC data structure consists of three elements: the APC parameter tables for the PHY devices, the APC priority table, and the APC scheduling tables. See Figure 29-38. 29-61 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 842: Apc Parameter Tables

    Byte 0x07 CPS_CNT Byte 0x08 MAX_ITERATIO Byte 0x09 CPS_ABR Byte 29-62 MPC8260 PowerQUICC II UserÕs Manual APC Priority Table Priority 1 Priority 2 Priority 3 Priority 4 Priority 5 Priority 6 Priority 7 Priority 8 Description as APCL_FIRST + 8 x (number_of_priorities - 1).

  • Page 843: Apc Priority Table

    Slot N+1 is used as a control slot, as shown in Figure 29-40. Bits Field TCTE 29-63 MPC8260 PowerQUICC II UserÕs Manual Description format. User-deÞned. Real-time stamp pointer used internally by the APC. Initialize to 0. Used internally by the APC. Initialize to 0.

  • Page 844: Atm Controller Buffer Descriptors (Bds)

    CP removes the channel from the APC and clears TCT[VCON]. The core must issue a command to restart transmission. ATM TRANSMIT Figure 29-41 shows the ready bit in the TxBD tables and their associated buffers for two example ATM channels. 29-64 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 845: Receive Buffers Operation

    Figure 29-42 shows the empty bit in the RxBD tables and their associated buffers for two example ATM channels. 29-65 MPC8260 PowerQUICC II UserÕs Manual Ch1 TxBD Table Tx Buffer 1 of Channel 1 BD 1...

  • Page 846: Global Buffer Allocation

    1. The CP allocates the Þrst two buffers of buffer pool 1 to channel 1 and the third to channel 4. 29-66 MPC8260 PowerQUICC II UserÕs Manual Ch1 RxBD Table Rx Buffer 1 of Channel 1...

  • Page 847: Free Buffer Pools

    FBP#_BASE Software (Core) Pointer FBP#_PTR Figure 29-44. Free Buffer Pool Structure Figure 29-45 describes the structure of a free buffer pool entry. 29-67 MPC8260 PowerQUICC II UserÕs Manual Ch1 RxBD Table RBD_BASE RBD_Offset Ch4 RxBD Table Buffer 4 RBD_BASE,...

  • Page 848: Free Buffer Pool Parameter Tables

    FBP_ENTRY_EXT Free buffer pool entry extension. FBP_ENTRY_EXT[0Ð3] holds the four left bits 0x0A BUSY 2Ð7 Ñ 29-68 MPC8260 PowerQUICC II UserÕs Manual Buffer Pointer (BP) Buffer Pointer (BP) Description Description Free buffer pool base. Holds the pointer to the Þrst entry in the free buffer pool.

  • Page 849: Atm Controller Buffers

    Ñ Offset + 0x02 Offset + 0x04 Offset + 0x06 29-69 MPC8260 PowerQUICC II UserÕs Manual Description Early packet discard. 0 Normal operation. 1 AAL5 frames in progress are received, but new AAL5 frames associated with this pool are discarded. Can be used to implement EPD under core control.
  • Page 850 47 or less than zero octets. Rx CRC error. Indicates CRC32 error in the current AAL5 PDU. Set only for the last BD of the frame. 29-70 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 851: Aal1 Rxbd

    29.10.5.5 AAL1 RxBD Figure 29-47 shows the AAL1 RxBD. Offset + 0x00 Ñ Offset + 0x02 Offset + 0x04 Offset + 0x06 29-71 MPC8260 PowerQUICC II UserÕs Manual Description Ñ Data Length Rx Data Buffer Pointer Figure 29-47. AAL1 RxBD Ñ MOTOROLA...

  • Page 852: Aal0 Rxbd

    Figure 29-48 shows the AAL0 RxBD. Offset + 0x00 Ñ Offset + 0x02 Offset + 0x04 Offset + 0x06 29-72 MPC8260 PowerQUICC II UserÕs Manual Description Ñ Ñ Data Length (DL)/Channel Code (CC) Rx Data Buffer Pointer (RXDBPTR) Figure 29-48. AAL0 RxBD Ñ...
  • Page 853 In user-deÞned cell mode, the AAL5 and AAL1 RxBDs are extended to 32 bytes; see Figure 29-49. Note that for AAL0, a complete cell, including the UDC header, is stored in the buffer; the AAL0 BD size is always 8 bytes. 29-73 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 854: Aal5 Txbds

    Ñ Offset + 0x02 Offset + 0x04 Offset + 0x06 29-74 Extra Cell Header. Reserved (12 bytes) Ñ Ñ Data Length (DL) Tx Data Buffer Pointer (TXDBPTR) Figure 29-50. AAL5 TxBD MPC8260 PowerQUICC II UserÕs Manual CLP CNG Ñ MOTOROLA...
  • Page 855 TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may not be 8-byte-aligned. The buffer may reside in either internal or external memory. This value is not modiÞed by the CP. 29-75 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 856: Aal1 Txbds

    TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may reside in either internal or external memory. This value is not modiÞed by the CP. 29-76 MPC8260 PowerQUICC II UserÕs Manual Ñ Data Length (DL) Tx Data Buffer Pointer (TXDBPTR) Figure 29-51.

  • Page 857: Aal0 Txbds

    TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may not be 8-byte-aligned. The buffer may reside in either internal or external memory. This value is not modiÞed by the CP. 29-77 MPC8260 PowerQUICC II UserÕs Manual Ñ Ñ Ñ...

  • Page 858: Aal1 Sequence Number (Sn) Protection Table (Aal1 Only)

    UNI statistics parameters. UNI_STATT_BASE points to the base address of this table. Each PHY has its own table with a starting address given by UNI_STATT_BASE+ PHY# ´ 8. 29-78 MPC8260 PowerQUICC II UserÕs Manual Extra Cell Header. Reserved (12 bytes) 0x0000...

  • Page 859: Atm Exceptions

    Þrst entry in the queue. If the CP tries to overwrite a valid entry (V = 1), an overßow condition occurs and the queueÕs overßow ßag, FCCE[INTOx], is set. 29-79 MPC8260 PowerQUICC II UserÕs Manual Description Counts cells dropped as a result of UTOPIA parity error or state machine errors (short or long cells).

  • Page 860: Interrupt Queue Entry

    Each one-word interrupt queue entry provides detailed interrupt information to the host. Figure 29-56 shows an entry. Offset + 0x00 Ñ Offset + 0x02 Figure 29-56. Interrupt Queue Entry 29-80 MPC8260 PowerQUICC II UserÕs Manual Word V = 0 W = 0 V = 0 W = 0 V = 0...

  • Page 861: Interrupt Queue Parameter Tables

    Half Word Interrupt counter. Initialize with INT_ICNT. The CP decrements INT_CNT for 0x0A INT_ICNT Half Word Interrupt initial count. User-deÞned global interrupt thresholdÑthe number of 29-81 MPC8260 PowerQUICC II UserÕs Manual Description Description Base address of the interrupt queue. User-deÞned. Pointer to interrupt queue entry. Initialize to INTQ_BASE.

  • Page 862: The Utopia Interface

    29.12 The UTOPIA Interface The ATM controller interfaces with a PHY device through the UTOPIA interface. The MPC8260 supports UTOPIA level 2 for both master and slave modes. 29.12.1 UTOPIA Interface Master Mode UTOPIA master signals are shown in Figure 29-57.

  • Page 863: Utopia Master Multiple Phy Operation

    29.12.1.1 UTOPIA Master Multiple PHY Operation The cell transfer in a multiple PHY ATM port uses cell-level handshaking as deÞned in the UTOPIA standards. The MPC8260 supports two polling modes: ¥ Direct polling uses CLAV[0Ð3] with PHY selection using ADD[0Ð2]. Up to four PHYs can be supported.

  • Page 864: Utopia Slave Multiple Phy Operation

    FPSMR[PHY ID]. 29.12.2.2 UTOPIA Clocking Modes The UTOPIA clock is generated by one of the MPC8260Õs baud-rate generators. The user should assign one of the baud rate generators to supply the UTOPIA clock. See Chapter 15, ÒCPM Multiplexing.Ó...

  • Page 865: Utopia Loop-Back Modes

    The FCC protocol-speciÞc mode register (FPSMR), shown in Figure 29-59, controls various protocol-speciÞc FCC functions. The user should initialize the FPSMR. Erratic behavior may result if there is an attempt to write to the FPSMR while the transmitter and receiver are enabled. 29-85 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...
  • Page 866 Transmit user-deÞned cells 0 Regular 53-byte cells. 1 User-deÞned cells. RUDC Receive user-deÞned cells 0 Regular 53-byte cells. 1 User-deÞned cells. 29-86 MPC8260 PowerQUICC II UserÕs Manual REHS TUMS RUMS 0000_0000_0000_0000 Ñ TSIZE RSIZE UPRM UPLM RUMP HECI 0000_0000_0000_0000 Description LAST PHY/PHY ID Ñ...

  • Page 867: Atm Event Register (Fcce)/Mask Register (Fccm)

    FCCM is the ATM controller mask register. It is a 16-bit read/write register with the same bit format as FCCE. If an FCCM bit is set, the corresponding interrupt is enabled in FCCE. If it is cleared, the corresponding interrupt is masked. FCCM is cleared at reset. 29-87 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 868: Fcc Transmit Internal Rate Registers (Ftirrx)

    CMXUAR; see Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó Note that in slave mode, FTIRRx_PHY0 is used regardless of the slave PHY address. 29-88 MPC8260 PowerQUICC II UserÕs Manual 0000_0000_0000_0000 Description MOTOROLA...
  • Page 869 Figure 29-62. FCC Transmit Internal Rate Clocking Example: Suppose the MPC8260 is connected to four 155 Mbps PHY devices and the maximum transmission rate is 155 Mbps for the Þrst PHY and 10 Mbps for the rest of the PHYs. The BRG CLK should be set according to the highest rate.

  • Page 870: Atm Transmit Command

    Burst tolerance. For use by VBR channels only (ACT Þeld is 0b01). SpeciÞes the initial burst tolerance (GCRA burst credit) of the current VC. 29-90 MPC8260 PowerQUICC II UserÕs Manual that can be sent to the CP command ATM TRANSMIT...

  • Page 871: Srts Generation And Clock Recovery Using External Logic

    The MPC8260 supports SRTS generation using external logic. If SRTS generation is enabled (TCT[SRT] = 1), the MPC8260 reads SRTS[0Ð3] from the external SRTS logic and inserts it into 4 cells whose SN Þelds equal 1, 3, 5, and 7, as shown in Figure 29-64.

  • Page 872: Using Transmit Internal Rate Mode

    Figure 29-65. AAL1 SRTS Clock Recovery Using External Logic On every eighth cell, the MPC8260 writes a new SRTS code to the external logic using the bus selected in RCT[BIB]. The CP writes the SRTS code using a DMA write cycle of 1- byte data size.
  • Page 873 BD. In static buffer allocation, the core assigns a Þxed data buffer to each BD. (See Section 29.10.5.2, ÒReceive Buffers Operation.Ó) When allowed by the application, use static buffer allocation to increase CPM performance. MOTOROLA Part IV. Communications Processor Module ´ ´...
  • Page 874 Part IV. Communications Processor Module 29-94 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 875: Fast Ethernet Controller

    When a station needs to transmit, it waits until the LAN becomes silent for a speciÞed period (interframe gap). When a station starts sending, it continually checks for collisions MOTOROLA Frame Length is 64Ð1,518 Bytes Source...

  • Page 876: Fast Ethernet On The Mpc8260

    ¥ The minimum interframe gap is 0.96 µs. ¥ The slot time is 5.12 µs. 30.1 Fast Ethernet on the MPC8260 When a general FCC mode register (GFMRx[MODE]) selects Ethernet protocol, that FCC performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control (MAC) and channel interface functions.

  • Page 877: Features

    Ñ Delay transmission of new frames for speciÞed interframe gap ¥ Bit rates up to 100 Mbps ¥ Receives back-to-back frames ¥ Detection of receive frames that are too long MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module Control...

  • Page 878: Connecting The Mpc8260 To Fast Ethernet

    30.3 Connecting the MPC8260 to Fast Ethernet Figure 30-3 shows the basic components of the media-independent interface (MII) and the signals required to make the Fast Ethernet connection between the MPC8260 and a PHY. 30-4 MPC8260 PowerQUICC II UserÕs Manual...

  • Page 879: Ethernet Channel Frame Transmission

    (CAM), which are described in Section 30.7, ÒCAM Interface.Ó The MPC8260 uses the SDMA channels to store every byte received after the start frame delimiter into system memory. On transmit, the user provides the destination address, source address, type/length Þeld, and transmit data. To meet minimum frame requirements, MPC8260 automatically pads frames with fewer than 64 bytes in the data Þeld.
  • Page 880 Þnishes or terminates with a collision. When the Ethernet controller is given the command, RESTART TRANSMIT it resumes transmission. The Ethernet controller sends bytes least-signiÞcant nibble Þrst. 30-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 881: Ethernet Channel Frame Reception

    When the receive frame is complete, the Ethernet controller sets RxBD[L], writes the other frame status bits into the RxBD, and clears RxBD[E]. The Ethernet controller next generates a maskable interrupt, indicating that a frame was received and is in memory. The MOTOROLA Chapter 30. Fast Ethernet Controller 30-7...

  • Page 882: Flow Control

    30.7 CAM Interface The MPC8260 internal address recognition logic can be used in combination with an external CAM. When using a CAM, the FCC must be in promiscuous mode (FPSMRx[PRO] = 1).

  • Page 883: Ethernet Parameter Ram

    RxBD. MFLR includes all in- frame bytes between the start frame delimiter and the end of the frame. MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module Description command is used to enable the hash table.
  • Page 884 (including the discarded bytes) in the last RxBD. This value must be greater than 32. 30-10 MPC8260 PowerQUICC II UserÕs Manual Description command enables the hash table. See SET GROUP ADDRESS SET GROUP ADDRESS command.
  • Page 885 Word (RMON mode only) The total number of packets (including bad packets) received that were between 65 and 127 octets long inclusive (excluding framing bits but including FCS octets). MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module...

  • Page 886: Programming Model

    Transmit commands that apply to Ethernet are described in Table 30-3. Table 30-3. Transmit Commands Command Description When used with the Ethernet controller, this command violates a speciÞc behavior of an Ethernet/IEEE STOP 802.3 station. It should not be used. TRANSMIT 30-12 MPC8260 PowerQUICC II UserÕs Manual Description NOTE MOTOROLA...
  • Page 887 This is required because the hash table might have mapped multiple addresses to the same hash table bit. MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module...

  • Page 888: Rmon Support

    The total number of packets received that were longer than 1518 octets (excluding framing bits but including FCS octets) and were otherwise well-formed. 30-14 MPC8260 PowerQUICC II UserÕs Manual Description Counter DISFC OCTC USPC + OSPC +...

  • Page 889: Ethernet Address Recognition

    The difference between an individual address and a group address is determined by the I/G bit in the destination address Þeld. Figure 30-4 is a ßowchart for address recognition on received frames. MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module...
  • Page 890 Part IV. Communications Processor Module Broadcast Addr Hash Search Use Group Broadcast Enabled Discard Frame Figure 30-4. Ethernet Address Recognition Flowchart 30-16 MPC8260 PowerQUICC II UserÕs Manual Check Address I/G Address Hash Search Use Individual Table Table Receive Frame Promiscuous?

  • Page 891: Hash Table Algorithm

    In such instances, an external CAM is advised if the extra bus use cannot be tolerated. See Section 30.7, ÒCAM Interface.Ó MOTOROLA Chapter 30. Fast Ethernet Controller 30-17...

  • Page 892: Interpacket Gap Time

    The transmitted data from the transmit FIFO is received immediately into the receive FIFO. There is no heartbeat check in this mode. In external loopback operation, the Ethernet controller listens for data received from the PHY while it is sending. 30-18 MPC8260 PowerQUICC II UserÕs Manual NOTE MOTOROLA...

  • Page 893: Ethernet Error-Handling Procedure

    30.18 Fast Ethernet Registers The following sections describe registers used for conÞguring and operating the Fast Ethernet controller. MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module Response command.

  • Page 894: Fcc Ethernet Mode Register (Fpsmr)

    1 The controller forces a collision on transmission of every transmit frame. The MPC8260 should be conÞgured in loopback operation when using this feature, which allows the user to test the MPC8260 collision logic. It causes the retry limit to be exceeded for each transmit frame.

  • Page 895: Ethernet Event Register (Fcce)/Mask Register (Fccm)

    The FCCM has the same bit format as FCCE. Setting an FCCM bit enables and clearing a bit masks the corresponding interrupt in the FCCE. The FCCE can be read at any time. Bits are cleared by writing ones; writing zeros does not MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module...
  • Page 896 Rx buffer. A buffer that was not a complete frame is received on the Ethernet channel. Figure 30-7 shows interrupts that can be generated in the Ethernet protocol. 30-22 MPC8260 PowerQUICC II UserÕs Manual GRA RXC TXC TXE RXF BSY TXB RXB 0000_0000_0000_0000...

  • Page 897: Ethernet Rxbds

    30.19 Ethernet RxBDs The Ethernet controller uses the RxBD to report information about the received data for each buffer. Figure 30-8 shows the FCC Ethernet RxBD format. MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module Stored in Rx Buffer...
  • Page 898 Multicast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address is a multicast address other than a broadcast address. 30-24 MPC8260 PowerQUICC II UserÕs Manual Ñ Data Length Rx Data Buffer Pointer...
  • Page 899 Note that at least two BDs must be prepared before beginning reception. Figure 30-9 shows how RxBDs are used during Ethernet reception. MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module...

  • Page 900: Ethernet Txbds

    TxBD table. The Ethernet controller uses TxBDs to conÞrm transmission or indicate errors so the core knows when buffers have been serviced. Figure 30-10 shows the FCC Ethernet TxBD format. 30-26 MPC8260 PowerQUICC II UserÕs Manual MRBLR = 64 Bytes for this FCC Buffer Destination Address (6)
  • Page 901 The Ethernet controller terminates the transmission and updates LC after sending the buffer. Retransmission limit. The transmitter failed (RET_LIM + 1) attempts to successfully send a message due to repeated collisions. The Ethernet controller updates RL after sending the buffer. MOTOROLA Chapter 30. Fast Ethernet Controller Part IV. Communications Processor Module...
  • Page 902 Tx data buffer pointer, which contains the address of the associated data buffer, can be even or odd. The buffer can reside in internal or external memory. The CP never modiÞes the buffer pointer. 30-28 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 903: Fcc Hdlc Controller

    FCCs. The user can allocate external buffer descriptors (BDs) for receive and transmit tasks so many frames can be sent or received without core intervention. MOTOROLA Chapter 31. FCC HDLC Controller 31-1...

  • Page 904: Key Features

    I bit in the TxBD is set. The HDLC controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted after each buffer, after a speciÞc buffer, after each frame, or after a number of frames. 31-2 MPC8260 PowerQUICC II UserÕs Manual Control Information (Optional) 8 Bits...

  • Page 905: Hdlc Channel Frame Reception Processing

    This is conÞgured in the received frames threshold (RFTHR) location of the parameter RAM. This function can be combined with a timer to implement a time-out if fewer than the threshold number of frames are received. MOTOROLA Chapter 31. FCC HDLC Controller 31-3...

  • Page 906: Hdlc Parameter Ram

    Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 13.5.2, ÒParameter RAM.Ó DISFC, CRCEC, ABTSC, and NMARCÑThese 16-bit (modulo 216) counters are maintained by the CP. The user can initialize them while the channel is disabled. 31-4 Description MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 907: Programming Model

    FCCE[GRA] is set once transmission has stopped. Then the HDLC transmit parameters TRANSMIT (including BDs) can be modiÞed. The TBPTR points to the next TxBD in the table. Transmission begins once the R bit of the next BD is set and the MOTOROLA Part IV. Communications Processor Module Control Flag etc.

  • Page 908: Hdlc Error Handling

    When this error occurs, the channel terminates buffer transmission, closes the buffer, sets TxBD[CT], during Frame and generates a TXE interrupt (if it is enabled). The channel resumes transmission after receiving Transmission RESTART TRANSMIT 31-6 MPC8260 PowerQUICC II UserÕs Manual Description command, after a STOP TRANSMIT GRACEFUL STOP TRANSMIT Description Description command.

  • Page 909: Hdlc Mode Register (Fpsmr)

    31.6 HDLC Mode Register (FPSMR) When an FCC is conÞgured for HDLC mode, the FPSMR is used as the HDLC mode register, shown in Figure 31-3. MOTOROLA Part IV. Communications Processor Module Description Valid data Chapter 31.
  • Page 910 Reserved, should be cleared. 0 nibble mode disabled (1 bit of data per clock). 1 nibble mode (4 bits of data per clock). 17Ð23 Ñ Reserved, should be cleared. 31-8 MPC8260 PowerQUICC II UserÕs Manual FSE MFF Ñ 0000_0000_0000_0000 Ñ 0000_0000_0000_0000 Description Ñ...

  • Page 911: Hdlc Receive Buffer Descriptor (Rxbd)

    31.7 HDLC Receive Buffer Descriptor (RxBD) The HDLC controller uses the RxBD to report on data received for each buffer. Figure 31-4 shows an example of the RxBD process. MOTOROLA Part IV. Communications Processor Module Description Chapter 31. FCC HDLC Controller...
  • Page 912 C = Control Byte I = Information Byte CR = CRC Byte Figure 31-4. FCC HDLC Receiving Using RxBDs 31-10 MPC8260 PowerQUICC II UserÕs Manual MRBLR = 32 Bytes for this FCC Address 1 Address 2 Buffer Full Control Byte...
  • Page 913 RxBD is closed, the RXF bit is set, and the closing ßag is received. The number of bytes received between ßags is written to the data length Þeld of this BD. MOTOROLA Part IV. Communications Processor Module Ñ...

  • Page 914: Hdlc Transmit Buffer Descriptor (Txbd)

    Figure 31-6 shows the FCC HDLC TxBD. Offset + 0 Ñ Offset + 2 Offset + 4 Offset + 6 Figure 31-6. FCC HDLC Transmit Buffer Descriptor (TxBD) 31-12 MPC8260 PowerQUICC II UserÕs Manual Description Data Length Tx Data Buffer Pointer Ñ MOTOROLA...
  • Page 915 FIFO buffer when this error occurs, CT is set in the currently open TxBD. The HDLC controller writes CT after sending the buffer. The TxBD status bits are written by the HDLC controller after sending the associated data buffer. MOTOROLA Part IV. Communications Processor Module Description Chapter 31. FCC HDLC Controller...

  • Page 916: Hdlc Event Register (Fcce)/Mask Register (Fccm)

    0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/ 0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3) Figure 31-7. HDLC Event Register (FCCE)/Mask Register (FCCM) Table 31-9 describes FCCE/FCCM Þelds. 31-14 MPC8260 PowerQUICC II UserÕs Manual 0000_0000_0000_0000 25 26 0000_0000_0000_0000 Ñ TXE RXF BSY TXB RXB Ñ...
  • Page 917 The real-time status can be read in FCCS; see Section 31.10, ÒFCC Status Register (FCCS).Ó 24Ð31 Ñ Reserved, should be cleared. Figure 31-8 shows interrupts that can be generated in the HDLC protocol. MOTOROLA Part IV. Communications Processor Module Description Chapter 31. FCC HDLC Controller GRACEFUL STOP TRANSMIT...

  • Page 918: Fcc Status Register (Fccs)

    Bits Field Reset Addr 0x11318 (FCCS1), 0x11338 (FCCS2), 0x11358 (FCCS3) Figure 31-9. FCC Status Register (FCCS) 31-16 MPC8260 PowerQUICC II UserÕs Manual Stored in Rx Buffer I CR CR F Stored in Tx Buffer C CR CR F Ñ 0000_0000...
  • Page 919 Idle status. ID is set when the RXD signal is a logic one for 15 or more consecutive bit times; it is cleared after a logic zero is received. 0 The line is busy. 1 The line is idle. MOTOROLA Part IV. Communications Processor Module Description Chapter 31. FCC HDLC Controller...
  • Page 920 Part IV. Communications Processor Module 31-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 921: Fcc Transparent Controller

    Þrst in each octet. The FCC consists of separate transmit and receive sections whose operations are asynchronous with the core and can either be synchronous or asynchronous with respect to the other FCCs. Each clock can be supplied from the internal BRG bank or external signals. MOTOROLA Chapter 32. FCC Transparent Controller 32-1...

  • Page 922: Features

    The synchronization process gives the user bit-level control of when the transmission and reception begins. The methods for this are as follows: ¥ An in-line synchronization pattern ¥ External synchronization signals ¥ Automatic sync 32-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

  • Page 923: In-Line Synchronization Pattern

    This option allows the RTS of one FCC to be connected to the CD of another FCC (on another MPC8260) and to have the data synchronized and bit aligned. It is also an option to link the transmitter synchronization to the receiver synchronization.

  • Page 924: Transparent Synchronization Example

    (Output is CD Input) Notes: 1. Each MPC8260 generates its own transmit clocks. If the transmit and receive clocks are the same, one can generate transmit and receive clocks for the other MPC8260. For example, CLKx on MPC8260 (B) could be used to clock the transmitter and receiver.

  • Page 925: Serial Peripheral Interface (Spi)

    Chapter 33 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the MPC8260 to exchange data between other MPC8260 chips, the MPC860, the MC68360, the MC68302, the M68HC11 and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.

  • Page 926: Features

    SPI signal is driven by the MPC8260 or an external SPI device. The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an output for slave devices.

  • Page 927: The Spi As A Master Device

    In master mode, the SPI sends a message to the slave peripheral, which sends back a simultaneous reply. A single master MPC8260 with multiple slaves can use general- purpose parallel I/O signals to selectively enable slaves, as shown in Figure 33-2. To eliminate the multimaster error in a single-master environment, the masterÕs SPISEL input...

  • Page 928: The Spi As A Slave Device

    SPI device is a bus master. The SPI sets SPIE[MME] in the SPI event register and a maskable interrupt is issued to the core. It also disables SPI operation and the output 33-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 929 ¥ It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example) ¥ SELOUTx signals are implemented in software with general-purpose I/O signals Figure 33-3. Multimaster Configuration MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) Part IV. Communications Processor Module MPC8260 SPI #0 SPIMOSI SPIMISO SPICLK SPISEL...

  • Page 930: Programming The Spi Registers

    1 Normal operationÑmsb of the character sent and received Þrst. Master/slave. Selects master or slave mode. 0 The SPI is a slave. 1 The SPI is a master. 33-6 MPC8260 PowerQUICC II UserÕs Manual DIV16 REV — 0x11AA0 Description 0_0000_0000...
  • Page 931 (CI = 0) SPICLK (CI = 1) SPIMOSI (From Master) SPIMISO (From Slave) SPISEL NOTE: Q = Undefined Signal. Figure 33-6. SPI Transfer Format with SPMODE[CP] = 1 MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) Part IV. Communications Processor Module Description 33-7...

  • Page 932: Spi Examples With Different Spmode[Len] Values

    REV=1, the string is byte reversed and transmitted, a byte at a time, with lsb first: first Example 3: with LEN=0xC (data size=13), the following data is selected: 33-8 MPC8260 PowerQUICC II UserÕs Manual Binary symbols Deleted bit Original byte boundary Original 4-bit boundary. ghij_klmn__opqr_stuv...

  • Page 933: Spi Event/Mask Registers (Spie/Spim)

    Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed. 33.4.3 SPI Command Register (SPCOM) The SPI command register (SPCOM), shown in Figure 33-8, is used to start SPI operation. MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) Part IV. Communications Processor Module...

  • Page 934: Spi Parameter Ram

    Rx/Tx function code registers. The function code registers contain the transaction speciÞcation associated with SDMA channel accesses to external memory. See 0x05 TFCR Byte Section 33.5.1, ÒReceive/Transmit Function Code Registers (RFCR/TFCR).Ó 33-10 MPC8260 PowerQUICC II UserÕs Manual Ñ 0000_0000 Write Only 0x11AAD Description Description...
  • Page 935 MRBLR Hword Maximum receive buffer length. The SPI has one MRBLR entry to deÞne the maximum number of bytes the MPC8260 writes to a Rx buffer before moving to the next buffer. The MPC8260 can write fewer bytes than MRBLR if an error or end-of-frame occurs, but never exceeds the MRBLR value.

  • Page 936: Receive/Transmit Function Code Registers (Rfcr/Tfcr)

    CLOSE RXBD If the controller is not receiving data, no action is taken. Use this command to extract data from a partially full buffer. 33-12 MPC8260 PowerQUICC II UserÕs Manual 0000_0000 SPI Base + 04 (RFCR)/SPI Base + 05 (TFCR) Description Table 33-7.

  • Page 937: The Spi Buffer Descriptor (Bd) Table

    Ñ For a TxBD, this is the number of octets the CP should transmit from its buffer. Normally, this value should be greater than zero. If the character length is more MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) Part IV. Communications Processor Module...

  • Page 938: Spi Receive Bd (Rxbd)

    0 No interrupt is generated after this buffer is Þlled. 1 SPIE[RXB] is set when this buffer is full, indicating the need for the core to process the buffer. SPIE[RXB] causes an interrupt if not masked. 33-14 MPC8260 PowerQUICC II UserÕs Manual Ñ Data Length Rx Buffer Pointer Figure 33-11.

  • Page 939: Spi Transmit Bd (Txbd)

    RxBD[CM] is set) after the buffer is sent (unless RxBD[CM] is set) or an error occurs. 1 The buffer is ready for transmission or is being sent. The BD cannot be modiÞed once R is set. Ñ Reserved, should be cleared. MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) Part IV. Communications Processor Module Description Ñ...

  • Page 940: Spi Master Programming Example

    16 bytes, so MRBLR = 0x0010. 7. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. 33-16 MPC8260 PowerQUICC II UserÕs Manual Description MOTOROLA...

  • Page 941: Spi Slave Programming Example

    12. Set SPCOM[STR] to enable the SPI to be ready once the master begins the transfer. Note that if the master sends 3 bytes and negates SPISEL, the RxBD is closed but the TxBD MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) Part IV.

  • Page 942: Handling Interrupts In The Spi

    SPIE bits should be cleared at this time. 2. Process the TxBD to reuse it and the RxBD to extract the data from it. To transmit another buffer, simply set TxBD[R], RxBD[E], and SPCOM[STR]. 3. Execute an rÞ instruction. 33-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 943 SCL stays low to generate bus timeouts. Rx Data Register Shift Register Figure 34-1. I MOTOROLA C¨) controller lets the MPC8260 exchange data with other C controller consists of transmit and receive sections, an C BRG when in master mode and Peripheral Bus Tx Data Register...

  • Page 944: Features

    When the bus is free, both signals are pulled high. The general I master/slave conÞguration is shown in Figure 34-2. Master Figure 34-2. I 34-2 MPC8260 PowerQUICC II UserÕs Manual C mode register (I2MOD[EN] = 0), it consumes C controllerÕs main features: C operation C BRG takes its input from the BRG...

  • Page 945: C Controller Transfers

    TxBD without waiting for I2COM[STR] to be set again. The following sections further detail the transfer process. MOTOROLA Part IV. Communications Processor Module C controller sends a message specifying a read or write...

  • Page 946: C Master Write (Slave Read)

    Initialize the Þrst transmit data byte with the slave address and write request (R/W = 0). If the MPC8260 is the slave target of the write, prepare receive buffers and BDs to await the masterÕs request. Figure 34-4 shows the timing for a master write.

  • Page 947: C Multi-Master Considerations

    2. The slave detects a start condition on SDA and SCL. 3. After the Þrst byte is shifted in, the slave compares the received data to its slave address. If the slave is an MPC8260, the address is programmed in its I register (I2ADD).

  • Page 948: C Registers

    Problems could also arise if the MPC8260's I and BD for a write request, but then is the target of a read request from another master.

  • Page 949: C Address Register (I2Add)

    C baud rate generator register, shown in Figure 34-8, sets the divide ratio of the I BRG. Field Reset Addr Figure 34-8. I MOTOROLA Part IV. Communications Processor Module Description C is in a reset state and consumes minimal power. 0000_0000 0x11864...

  • Page 950: C Event/Mask Registers (I2Cer/I2Cmr)

    34.4.5 I C Command Register (I2COM) The I C command register, shown in Figure 34-10, is used to start I master or slave mode. 34-8 MPC8260 PowerQUICC II UserÕs Manual Description Ñ 0000_0000 0x11870(I2CER)/0x11874 I2CMR) C Event/Mask Registers (I2CER/I2CMR) Description C clock generator.

  • Page 951: C Parameter Ram

    Rx/Tx function code registers. The function code registers contain the transaction speciÞcation associated with SDMA channel accesses to external memory. See 0x05 TFCR Byte Figure 34-11 and Table 34-7. MOTOROLA Part IV. Communications Processor Module Ñ 0000_0000 0x1186C C Command Register (I2COM)
  • Page 952 Hword Maximum receive buffer length. DeÞnes the maximum number of bytes the MPC8260 writes to a Rx buffer before moving to the next buffer. The MPC8260 writes fewer bytes to the buffer than the MRBLR value if an error or end-of-frame occurs. Buffers should not be smaller than MRBLR.

  • Page 953: C Commands

    Initializes all receive parameters in the parameter RAM to their reset state. Should be issued only when INIT RX the receiver is disabled. The PARAMETERS Tx and Rx parameters. MOTOROLA Part IV. Communications Processor Module 0000_0000 I2C_BASE + 04 (RFCR)/I2C_BASE + 05 (TFCR) C Function Code Registers (RFCR/TFCR)

  • Page 954: The I C Buffer Descriptor (Bd) Table

    Ñ For an RxBD, the pointer must be even and can point to internal or external memory. Ñ For a TxBD, the pointer can be even or odd. The buffer can reside in internal or external memory. 34-12 MPC8260 PowerQUICC II UserÕs Manual TxBD Table Status and Control Data Length Buffer Pointer...

  • Page 955: C Receive Buffer Descriptor (Rxbd)

    Reserved and should be cleared. Overrun. Set when a receiver overrun occurs during reception. The I the received data is placed into the associated buffer. Ñ Reserved and should be cleared. MOTOROLA Part IV. Communications Processor Module C controller is enabled. Ñ Data Length RX Buffer Pointer Figure 34-13.

  • Page 956: C Transmit Buffer Descriptor (Txbd)

    Collision. Indicates that transmission terminated because the transmitter was lost while arbitrating for the bus. The I C controller updates CL after the buffer is sent. 34-14 MPC8260 PowerQUICC II UserÕs Manual Ñ Data Length Tx Buffer Pointer Figure 34-14. I...

  • Page 957: Parallel I/O Ports

    Note that port pins do not have internal pull-up resistors. Due to the CPMÕs signiÞcant ßexibility, many dedicated peripheral functions are multiplexed onto the ports. The functions are grouped to maximize the pinsÕ usefulness in the greatest number of MPC8260 applications. The reader may not obtain a full understanding of the pin assignment capability described in this chapter without understanding the CPM peripherals.

  • Page 958: Port Registers

    In this case, when PDATx is read, the port pin itself is read. If a port pin is conÞgured as an input, data written 35-2 MPC8260 PowerQUICC II UserÕs Manual OD4 OD5 OD6 OD7 OD8 OD9 OD10 OD11 OD12 OD13 OD14 OD15 0000_0000_0000_0000...

  • Page 959: Port Data Direction Registers (Pdiraðpdird)

    Direction. Indicates whether a pin is used as an input or an output. Note that bits DR0ÐDR3 are valid for PDIRA and PDIRC only. 0 The corresponding pin is an input. 1 The corresponding pin is an output. MOTOROLA Part IV. Communications Processor Module Ñ Ñ...

  • Page 960: Port Pin Assignment Register (Ppar)

    PDIR. 35.2.5 Port Special Options Registers AÐD (PSORAÐPSORD) Figure 35-5 shows the port special options registers (PSORx). 35-4 MPC8260 PowerQUICC II UserÕs Manual DD9 DD10 DD11 DD12 DD13 DD14 DD15 0000_0000_0000_0000 0000_0000_0000_0000...
  • Page 961 If the corresponding PPARx[DDx] = 1 (conÞgured as a general-purpose pin) before programming a PSORx or PDIRx bit, a pin might function for a short period as an unwanted dedicated function and cause unknown behavior. MOTOROLA Part IV. Communications Processor Module SO9 SO10 SO11 SO12 SO13 SO14 SO15...

  • Page 962: Port Block Diagram

    Bidirectional signals must be programmed as inputs (PDIR = 0). Figure 35-6. Port Functional Operation 35.4 Port Pins Functions Each pin can operate as a general purpose I/O pin or as a dedicated input or output pin. 35-6 MPC8260 PowerQUICC II UserÕs Manual Read PDATx Write PDATx Read PDATx...

  • Page 963: General Purpose I/O Pins

    As shown in Figure 35-7, some input functions can come from two different pins for ßexibility. Secondary option programming is relevant only if primary option is programmed to the default value. MOTOROLA Part IV. Communications Processor Module NOTE Chapter 35. Parallel I/O Ports...
  • Page 964 PA26 FCC1: RxClav FCC1: RxClav UTOPIA slave UTOPIA master FCC1: RxClav0 MPHY, master, direct 35-8 MPC8260 PowerQUICC II UserÕs Manual Primary option for SMC2 RxD Pin PA8 PPARA[8] == 1 & PSORA[8] == 0 & PDIRA[8] == 0 Pin Function...
  • Page 965 MII/HDLC/transp nibble PA19 FCC1: TxD[6] UTOPIA 8 FCC1: TxD[14] UTOPIA 16 FCC1: TxD[1] MII/HDLC/transp nibble MOTOROLA Part IV. Communications Processor Module Pin Function Default PDIRA = 1 (Output) Input MSNUM[0] MSNUM[1] Chapter 35. Parallel I/O Ports PSORA = 1 PDIRA = 0 (Input, or Default Inout if SpeciÞed)
  • Page 966 PA14 FCC1: RxD[4] FCC1: RxD[12] UTOPIA 16 FCC1: RxD[3] MII/HDLC/transp PA13 FCC1: RxD[3] FCC1: RxD[11] UTOPIA 16 35-10 MPC8260 PowerQUICC II UserÕs Manual Pin Function Default PDIRA = 1 (Output) Input UTOPIA 8 nibble UTOPIA 8 nibble UTOPIA 8 nibble...
  • Page 967 MSNUM[0Ð4] is the sub-block code of the peripheral controller using SDMA; MSNUM[5] indicates which section, transmit or receive, is active during the transfer. See Section 18.2.4, ÒSDMA Transfer Error MSNUM Registers (PDTEM and LDTEM).Ó MOTOROLA Part IV. Communications Processor Module Pin Function...
  • Page 968 MII/HDLC/transp. nibble FCC2: TxD HDLC/transp. serial PB21 FCC2: RxD[7] FCC2: RxD[0] MII/HDLC/transp. nibble FCC2: RxD HDLC/transp.. serial 35-12 MPC8260 PowerQUICC II UserÕs Manual Pin Function Default PDIRB = 1 (Output) Input UTOPIA FCC2: TX_EN SCC1: TXD TDM_A1: L1TXD[3] Nibble Nibble...
  • Page 969 MII/HDLC/transp. nibble FCC2: TxD[2] FCC3: RxD[1] UTOPIA 8 MII/HDLC/transp. nibble FCC2: TxD[3] FCC3: RxD[0] UTOPIA 8 MII/HDLC/transp. nibble HDLC/transp. serial MOTOROLA Part IV. Communications Processor Module Pin Function Default PDIRB = 1 (Output) Input TDM_A1-L1TXD[1] UTOPIA 8 Nibble nibble TDM_D2: L1RQ...
  • Page 970 PC29 BRG2: BRGO PC28 Timer2: TOUT PC27 FCC3: TxD HDLC/transp. serial FCC3: TxD[0] MII/HDLC/transp. nibble 35-14 MPC8260 PowerQUICC II UserÕs Manual Pin Function Default PDIRB = 1 (Output) Input TDM_A2: L1TXD[0] UTOPIA 8 PC10 Output, nibble UTOPIA 8 PC11 UTOPIA 8...
  • Page 971 SCC2: CLSN (primary option) PC12 SI1: L1ST3 SCC2: RENA PC11 TDM_D1: L1CLKO SCC3: CTS SCC3: CLSN (primary option) 35-15 MPC8260 PowerQUICC II UserÕs Manual Pin Function Default PDIRC = 1 (Output) Input CLK6 CLK7 BRG4: BRGO CLK8 Timer4: TOUT CLK9...
  • Page 972 Available only when the primary option for this function is not used. MPHY Address pins 3,4 (master mode) can come from FCC2, depending on CMXUAR programming. (See Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó). 35-16 MPC8260 PowerQUICC II UserÕs Manual Pin Function Default PDIRC = 1 (Output)
  • Page 973 FCC1: RxD[4] SCC3: TENA Ethernet PD22 FCC1: TxD[5] SCC4: RXD UTOPIA 16 PD21 SCC4: TXD FCC1: RxD[3] MOTOROLA Part IV. Communications Processor Module Pin Function Default PDIRD = 1 (Output) Input SCC1: TXD FCC1: RxAddr[3] MPHY, master, multiplexed polling FCC2: RxAddr[4]...
  • Page 974 SI1: L1ST2 PD11 TDMB2: L1RQ FCC2: RxD[0] (secondary option) PD10 TDMB2: L1CLKO FCC2: RxD[1] (secondary option) SMC1: SMTXD 35-18 MPC8260 PowerQUICC II UserÕs Manual Pin Function Default PDIRD = 1 (Output) Input BRG1: BRGO polling polling UTOPIA GRANT UTOPIA 8...

  • Page 975: Interrupts From Port C

    1. Write the corresponding PPARC bit with a 1 and PSORC bit with 0. 2. Write the corresponding PDIRC bit with a zero. 3. Set the SIEXR bit (in the interrupt controller) to determine which edges cause interrupts. MOTOROLA Part IV. Communications Processor Module Pin Function Default...
  • Page 976 SIEXR. Do not program the IDMAx-DREQ pins to assert external requests to the IDMA, unless the IDMA is used. Otherwise, erratic operation occurs. 35-20 MPC8260 PowerQUICC II UserÕs Manual Note Note MOTOROLA...

  • Page 977: Appendix A Register Quick Reference Guide

    See the Programming Environments Manual for more information. Condition register See the Programming Environments Manual Table A-2 lists SPRs deÞned by the PowerPC architecture implemented on the MPC8260. Table A-2. User-Level PowerPC SPRs SPR Number Decimal SPR [5Ð9] SPR [0Ð4] 00000...

  • Page 978: Powerpc Registersñsupervisor Registers

    01000 11101 TBU write 01000 11111 Any read (mftb) to this address causes an implementation-dependent software emulation exception. MPC8260 PowerQUICC II UserÕs Manual ted on the MPC8260 ar Comments See the Programming Environments Manual and MPC603e RISC Microprocessor UserÕs Manual...
  • Page 979 A.3 MPC8260-SpeciÞc SPRs Table A-2 and Table A-5 list SPRs speciÞc to the MPC8260. Supervisor-level registers are described in Table A-5. Table A-5. MPC8260-Specific Supervisor-Level SPRs SPR Number Decimal SPR[5Ð9] SPR[0Ð4] 11110 10000 11110 10001 11110 10010 11110 10011 11110...
  • Page 980 Appendixes MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 981 8-26 overview, 8-1 pipeline control, 8-26 port size device interfaces, 8-17 processor state signals, 8-32 PSDMR register, 10-21 single-MPC8260 bus mode, 8-2 TBST signal, 8-13 TCn signals, 8-13 terminology, 8-1 TESCRx registers, 10-33 TLBISYNC input, 8-33 TSIZn signals, 8-13...

  • Page 982: Bus Configuration

    Fast Ethernet, 30-3 FCC overview, 28-3 C controller, 34-1 IEEE 1149.1 test access port, 12-2 parallel I/O ports, 35-6 PLL block diagram, 9-5 SCC block diagram, 19-2 serial interface, 14-2 serial peripheral interface (SPI), 33-1 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 983 UART mode serial communications controllers (SCCs), 20-15 serial management controllers (SMCs), 26-14 Bus interface hierarchical bus interface example, 10-100 BxTx (byte-select signals), 10-75 MOTOROLA INDEX Byte stuffing, 22-1 Byte-select signals, 10-75 Cascaded mode, 17-3 CHAMR (channel mode register), 27-10 CHAMR (channel mode register,...
  • Page 984 VCI/VPI address lookup, 29-14 VC-level address compression VP-level address compression table block diagram, 13-3 command set command descriptions, 13-14 command execution latency, 13-15 MPC8260 PowerQUICC II UserÕs Manual support, 29-27 (AAL5/AAL1), 29-73 (AAL5/AAL1), 29-78 tables (VCLT), 29-18 (VPLT), 29-17 MOTOROLA...
  • Page 985 RAM, 13-17 fast communications controllers (FCCs) Fast Ethernet mode address recognition, 30-15 block diagram, 30-3 CAM interface, 30-8 collision handling, 30-18 connecting to the MPC8260, 30-4 error handling, 30-19 FCCE, 30-21 FCCM, 30-21 features list, 30-3 FPSMR, 30-20 frame reception, 30-7...
  • Page 986 RTMR, 13-21 scan algorithm, 13-23 SET TIMER command, 13-22 table entries, 13-21 timer counts, comparing, 13-24 TM_CMD, 13-20 tracking CP loading, 13-24 SDMA channels bus arbitration, 18-2 bus transfers, 18-2 LDTEA, 18-4 LDTEM, 18-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 987 4-14 L_TESCR1, 4-38 L_TESCR2, 4-39 LCL_ACR, 4-29 LCL_ALRH, 4-30 LCL_ALRL, 4-30 MOTOROLA INDEX local bus monitor function, 4-2 masking interrupt sources, 4-13 MCC relative priority, 4-12 periodic interrupt timer (PIT), 4-5 periodic interrupt timer (PIT) function, 4-2...
  • Page 988 13-17 memory map, 13-16 overview, 13-15 parameter RAM, 13-17 EAMUX (external address multiplexing) signal, 10-41 EDO interface connection, MPC8260 to 60x bus, 10-92 Ethernet mode fast communications controller (FCC) address recognition, 30-15 block diagram, 30-3 CAM interface, 30-8...
  • Page 989 14-33 programming, 14-33 support, 14-31 General-purpose chip-select machine (GPCM) common features, 10-6 differences between MPC8xx and MPC8260, 10-62 external access termination, 10-60 implementation differences with UPMs and SDRAM machine, 10-7 interface signals, 10-51 MPC8xx versus MPC8260, 10-62...
  • Page 990 18-12 single address transfers (fly-by), 18-11 transfers, 18-6 IDMA parameter RAM, 18-16 IDMR (IDMA mask registers), 18-22 MPC8260 PowerQUICC II UserÕs Manual C event register), 34-8 C mask register), 34-8 C command) register, 34-8 C mode) register, 34-6 MOTOROLA...
  • Page 991 10-61 controlling the timing of GPL1, GPL2, and CSx, 10-68 CSx timing example, 10-68 delayed read, 10-10 EDO interface connection, MPC8260 to 60x bus, 10-92 error checking and correction (ECC), 10-9 external master support, 10-101 external support, 10-11...
  • Page 992 10-77 address multiplexing, 10-77 clock timing, 10-67 common features, 10-6 data sample control, 10-77 data valid, 10-77 differences between MPC8xx and MPC8260, 10- DRAM configuration example, 10-79 EDO interface example, 10-92 exception requests, 10-66 hierarchical bus interface example, 10-100 implementation...
  • Page 993 23-3 Operations atomic bus operation, 10-10 digital phase-locked loop (DPLL) operation, 19-22 SMC buffer descriptor, 26-5 transparent operation, NMSI sychronization, 23-3 ORx (option registers), 10-16 MOTOROLA INDEX Parallel I/O ports block diagram, 35-6 features, 35-1 overview, 35-1 PDATx, 35-2 PDIRx, 35-3 pin assignments (port AÐport D), 35-8Ð35-19...
  • Page 994 FPSMR, 31-7 overview FCCEx, 28-14 FCCMx, 28-14 FCCSx, 28-14 FCRx, 28-13 FDSRx, 28-7 FPSMRx, 28-7 FTODRx, 28-7 GFMRx, 28-3 interrupts, 28-13 timing control, 28-15 GSMR AppleTalk mode, 25-3 overview, 19-3 HDLC mode PSMR, 21-7 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 995 PowerPC supervisor-level, A-2, A-3 user-level, A-1 PSMR AppleTalk mode, 25-4 BISYNC mode, 22-10 Ethernet mode, 24-15 overview, 19-9 MOTOROLA INDEX transparent mode, 23-9 UART mode, 20-13 quick reference guide, A-1 reset mode, 5-5 reset status, 5-4 RFCR, 19-15 RISC timer tables...
  • Page 996 RTER (RISC timer event register), 13-21 RTMR (RISC timer mask register), 13-21 RTSCR (RISC time-stamp control register), 13-9 RTSR (RISC time-stamp register), 13-10 SCC memory map, 3-9 SCCE (SCC event) register BISYNC mode, 22-15 HDLC mode, 21-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 997 22-1 memory map, 22-4 overview, 22-1 parameter RAM, 22-3 programming example, 22-18 programming the controller, 22-17 receiving synchronization sequence, 22-9 RxBD, 22-12 MOTOROLA INDEX sending synchronization sequence, 22-9 TxBD, 22-14 Ethernet mode address recognition, 24-11 collision handling, 24-13 commands, 24-10...
  • Page 998 26-13 features list, 26-11 features not supported by SMCs, 26-10 frame format, 26-11 message-oriented mode, 26-12 overview, 26-10 parameter RAM, 26-6 programming example, 26-19 reception process, 26-12 RxBD, 26-14 transmission process, 26-11 TxBD, 26-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...
  • Page 999 SIPNR_H (SIU high interrupt pending register), 4-21 SIPNR_L (SIU low interrupt pending register), 4-21 SIPRR (SIU interrupt priority register), 4-18 SIU memory map, 3-1 MOTOROLA INDEX SIUMCR (SIU module configuration register), 4-31 SIVEC (SIU interrupt vector register), 4-23 SMC memory map, 3-12...
  • Page 1000 TSIZn (transfer size) signals, 8-13 TSTATE (internal transmitter state) register, 27-9 TTn (transfer type) signals, 8-10 UART mode commands, 20-6 control character insertion, 20-10 data handling, character and message-based, 20-5 error reporting, 20-6 features list, 20-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA...

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