Halt Bus Cycle - Intel 80C186XL User Manual

BUS INTERFACE UNIT
3.5.4

HALT Bus Cycle

Suspending the CPU reduces device power consumption and potentially reduces interrupt latency
time. The HLT instruction initiates two events:
1. Suspends the Execution Unit.
2. Instructs the BIU to execute a HALT bus cycle.
After executing a HALT bus cycle, the BIU suspends operation until one of the following events
occurs:
•
An interrupt is generated.
•
A bus HOLD is generated.
•
A DMA request is generated.
•
A refresh request is generated.
Figure 3-25 shows the operation of a HALT bus cycle. The address/data bus either floats or drives
during T1, depending on the next bus cycle to be executed by the BIU. Under most instruction
sequences, the BIU floats the address/data bus because the next operation would most likely be
an instruction prefetch. However, if the HALT occurs just after a bus write operation, the ad-
dress/data bus drives either data or address information during T1. A19:16 continue to drive the
previous bus cycle information under most instruction sequences (otherwise, they drive the next
prefetch address). The BIU always operates in the same way for any given instruction sequence.
The Chip-Select Unit prevents a programmed chip-select from going active during a HALT bus
cycle. However, chip-selects generated by external decoder circuits must be disabled for HALT
bus cycles.
Table 3-5 lists the state of each pin after entering the HALT bus state.
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