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6.6.5
Host Base Address Register (HBAR)
In multiplexed bus modes, HBAR selects the base address where the host-side registers are
mapped into the host bus address space. The address from the host bus is compared with the
base address as programmed in the Base Address Register. An internal chip select is
generated if a match is found. Figure 6-11 shows how the chip-select logic uses HBAR.
15
14
13
—Reserved bit, read as 0, write to 0 for future compatibility.
Figure 6-10. Host Base Address Register (HBAR) (X:$FFFFC5)
Table 6-11. Host Base Address Register (HBAR) Bit Definitions
Bit Number
Bit Name
15–8
7–0
BA[10–3]
DSP Peripheral
12
11
10
9
Reset Value
0
Reserved. Write to 0 for future compatibility.
$80
Base Address
Reflect the base address where the host-side registers are mapped into
the bus address space.
HAD[0–7]
Latch
HAS
HA[8–10]
Base
Address
Register
Data Bus
Figure 6-11. Self Chip-Select Logic
Host Interface (HI08)
8
7
6
5
BA10 BA9
BA8
Description
A[3–7]
8 bits
DSP Core Programming Model
4
3
2
1
BA7
BA6
BA5
BA4
Chip select
0
BA3
6-17
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