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There is no programmable control for the preamble selection. The first sub-frame to
be transmitted (immediately after the DAX is enabled) is the beginning of a block,
and therefore it has a "Z" preamble. This is followed by the second sub-frame, which
has an "Y" preamble. After that, "X" and "Y" preambles are transmitted alternately
until the end of the block transfer (192 frames transmitted). See Figure 8-4 for an
illustration of the preamble sequence.
DAX
Enabled
Here
Z
Y
8.5.10
DAX Clock Multiplexer
The DAX clock multiplexer selects one of the clock sources and generates the biphase
clock (128 Fs) and shift clock (64 Fs). The clock source can be selected from the
following options (see also Section 8.5.4.4 on page 8-9).
• The internal DSP core clock—assumes 1024 Fs
• DAX clock input pin(ACI)—512 Fs
• DAX clock input pin(ACI)—384 Fs
• DAX clock input pin(ACI)—256 Fs
Figure 8-5 shows how each clock is divided to generate the biphase and bit shift
clocks.
DSP Core Clock
(1024
Fs)
ACI Pin
{256,384,512}
Fs
MOTOROLA
X
Y
X
Y
First Block (384 Sub-frames)
Figure 8-4 Preamble sequence
1/4
0
1
1/2
1
0
(XCS1 or XCS0)
2/3
XCS1
XCS0
Figure 8-5 Clock Multiplexer Diagram
DSP56012 User's Manual
Digital Audio Transmitter
DAX Internal Architecture
X
Y
Z
Y
X
Second Block
0
1/2
1
Y
AA0609k
Biphase
Clock
(128
Fs)
Bit Shift
Clock
1/2
(64
Fs)
AA0610
8-13
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