Ram Configurations; Table 3-4 Ram Configurations For The Dsp56309; Table 3-5 Memory Locations For Program Ram And Instruction Cache - Motorola DSP56309 User Manual

Memory Configuration
Memory Configurations
3.3.2

RAM Configurations

The RAM configurations for the DSP56309 appear in Table 3-4.

Table 3-4 RAM Configurations for the DSP56309

Bit Settings
MS
0
0
1
1
The actual memory locations for Program RAM and the instruction cache in the Program
memory space are determined by the MS and CE bits. Their addresses appear in
Table 3-5.

Table 3-5 Memory Locations for Program RAM and Instruction Cache

MS
3-8
Program
CE
RAM
0 20
1 19
0 24
1 23
CE
0 0
0 1
1 0
1 1
DSP56309UM/D
Memory Sizes (in K)
X data Y data
RAM RAM
7 7
7 7
5 5
5 5
Program RAM
Cache Location
Location
$0000Ð$4FFF
$0000Ð$4BFF $4C00Ð$4FFF
$0000Ð$5FFF
$0000Ð$5BFF $5C00Ð$5FFF
Cache
0
1
0
1
N/A
N/A
MOTOROLA