Page 1 SPARClite MB86860 Series User Manual Edition 1.1 - Jul. 29, 1999 Fujitsu Ltd.
Page 2 MB86860 Series Programming Manual The User Manual consists of Hardware Manual Edition 1.1 - Jul. 29, 1999 and Programming Manual Edition 1.0 - Jun. 22, 1999...
Page 3 MB86860 Series Hardware Manual SPARClite MB86860 Series Hardware Manual Edition 1.1 - Jul. 29, 1999 Fujitsu Ltd.
Page 4: Table Of Contents
MB86860 Series Hardware Manual Rev.1.1 Jul.29/’99 Fig 8-3 of Page 8-10 and Fig.8-4 of Page 8-11 DQ32, 33, 33, 34, …, 62 => DQ32, 33, 34, 35, …, 63 Page 8-12 Note is added. Contents 1. Summary ..................... 1-1 ....................1.1.
Page 5 MB86860 Series Hardware Manual 4.2.1. Summary....................4-2 4.2.2. Register Overview ..................4-2 4.2.3. Register Details..................4-3 4.3. Caches...................... 4-9 4.3.1. Summary....................4-9 4.3.2. Cache Memory Assignments..............4-9 4.3.3. Tag/Data Format..................4-10 4.3.4. Operating Functions................4-11 4.4. DSU (Debug Support Unit)................4-12 4.4.1.
Page 6 MB86860 Series Hardware Manual 7.3.1. Address Range Specifier Registers (ARSR0-5)..........7-2 7.3.2. Address Mask Registers (AMR0-5) ............. 7-2 7.3.3. Wait State Specifier Registers (WSSR0-5)........... 7-3 7.3.4. MEXC Parity Error Control Registers (MXPEF) ..........7-4 7.3.5. MEXC Parity Error Control Registers ............7-4 7.3.6.
Page 7: Introduction
MB86860 Series Hardware Manual 1. Summary 1.1. Introduction The MB8686 Series processors are high-end processors which conform to SPARC Architecture Manual Version 8. This Manual explains MB86860 Series Processor (MB86860/86861) specifications. When developing software for use by these processors reference should also be made to the following manuals: •...
Page 8: Sparclite Interface
MB86860 Series Hardware Manual • Auto and self-refresh supported • Parity functions supported 1.2.6. SPARClite Interface • 64-bit, 32-bit-16-bit and 8-bit data buses • Programmable Chip Select Generator Function (5-chip select) • Wait State Control Function which generates waits for each chip select •...
Page 9 MB86860 Series Hardware Manual Figure 1.1 MB8686x Processor Block Diagram...
Page 10 MB86860 Series Hardware Manual 2. Pins 2.1. Package Pin Assignments INDEX ‚ ` ‚ a ‚ b ‚ c ‚ d ‚ e ‚ f ‚ g ‚ i ‚ j ‚ k ‚ l ‚ m ‚ o ‚ q ‚ s ‚ t ‚ u ‚ v ‚ x AA AB AC AD AE AF 10 11 12 13 14...
Page 11: Pin Overview
MB86860 Series Hardware Manual 2.2. Pin Overview Att. - Input - Output - Non-connected - Internal Logic 2.5V Power Supply Pin VDDE - 3.3V Power Supply Pin for I/O - Internal Logic and common grant pins for I/O VDDP1 - Power Supply Pin for PLL inside CP Core VSSP1 - Grant pin for PLL inside CPU Core VDDP2...
Page 12 MB86860 Series Hardware Manual...
Page 13 MB86860 Series Hardware Manual (Table 2-2 MB86860 Pins continued) PKG Pin No. Left side PKG Pin No. Bottom side PKG Pin No. Right side PKG Pin No. Top side (Fj) (JEDEC) Pin name Att. (Fj) (JEDEC) Pin name Att. (Fj) (JEDEC) Pin name att.
Page 14: Mb86861 Pin Overview
MB86860 Series Hardware Manual 2.2.2. MB86861 Pin Overview Table 2-3 Pin Overview (MB86861) PKG Pin No. Left side PKG Pin No. Bottom side PKG Pin No. Right side PKG Pin No. Top side (Fj) (JEDEC) Pin name Att. (Fj) (JEDEC) Pin name Att.
Page 15 MB86860 Series Hardware Manual Table 2-4 Pin Overview (MB86861 continued) PKG Pin No. Left side PKG Pin No. Bottom side PKG Pin No. Right side PKG Pin No. Top side (Fj) (JEDEC) Pin name Att. (Fj) (JEDEC) Pin name Att. (Fj) (JEDEC) Pin name...
Page 16: Outer Package Dimension Drawing
MB86860 Series Hardware Manual 2.3. Outer Package Dimension Drawing...
Page 17: Explanation Of Pin Functions
MB86860 Series Hardware Manual 2.4. Explanation of Pin Functions 2.4.1. SPARClite Bus Signals The notations about bus grant in the explanation column in Table 2-5 all assume that the transparent access mode to SDRAM is enabled. Table 2-5 SPARClite BUS Signals Normal Pin Name In Bus Grant...
Page 18 MB86860 Series Hardware Manual In Sleep Mode O (V) (861) “H” or “L” level is output.
Page 19 MB86860 Series Hardware Manual Normal Pin Name In Bus Grant Explanation In Sleep Mode When the CPU has the Bus Right ASI<3:0> ASI output pin. Output is valid during bus cycle periods, as are addresses. In Bus Grant O(Z) High-Z Status. Not used in access transparent function. In Sleep Mode O(Z) High-Z Status.
Page 20 MB86860 Series Hardware Manual Normal Pin Name In Bus Grant Explanation In Sleep Mode In Bus Grant O(Z) High-Z Status. This signal is not used for access transparent control. In Sleep Mode O(Z) (860) High-Z Status. In Sleep Mode O(H) (861) Outputs inactive level “H”.
Page 21 MB86860 Series Hardware Manual Normal Pin Name In Bus Grant Explanation In Sleep Mode the timing in which the CPU opens buses is as shown below: Burst reads from cache areas: opens bus after burst transfer ends. (2) Cache area, but BMACK# is not returned for a BMREQ#: Opens bus upon completion of 4 single transfers.
Page 22 MB86860 Series Hardware Manual Normal Pin Name In Bus Grant Explanation In Sleep Mode When the CPU has the Bus Right LOCK# Bus lock signal. This signal asserts during execution of Atomic Load/Store instructions and indicates that the current transaction requires multiple transfers which cannot be split. When atomic instructions are executed, opens buses (asserts BGRNT#) when execution of instructions for bus requests (BREQ#) is completed, and thus use of this signal is not required when controlling bus rights in normal use configuration (BREQ#/BGRNT#).
Page 23: Sdram-If Signals
MB86860 Series Hardware Manual 2.4.2. SDRAM-IF Signals Table 2-6 SDRAM Signals Pin Name Normal Explanation In Sleep Mode In Normal Operation SCLK SDRAM clock output signal. Should be linked to SDRAM clock input. When the load is 4 pins or more it should be buffered by the Zero Propagation Delay Buffer which has built-in PLL. In Sleep Mode Outputs “L”.
Page 24: Interrupt Signals
MB86860 Series Hardware Manual 2.4.3. Interrupt Signals Table 2-7 Interrupt Signals Pin Name Explanation IRL<3:0> Interrupt input pins. This is a signal for inputting encoded interrupt levels. These pins are grouped asynchronous input signals, and are first communicated to the IU (Integer Unit) when the same level is detected twice at external clock rise.
Page 25 MB86860 Series Hardware Manual Use prohibited Use prohibited 2-16...
Page 26: Test Signals
MB86860 Series Hardware Manual 2.4.6. Test Signals Table 2-11 Test Signals Pin Name Explanation FLOAT# Pin float input. By fixing this pin to “L”, all output pins and bi-directional pins except SDRAM-IF are set to High-Z status. BEN# PLL bypass enable input. When this signal is “L”, PLL bypass mode is effective. Should normally be fixed to “H”...
Page 27: Registers
MB86860 Series Hardware Manual 3. Registers MB8686 processor register settings can be classified into the following 3 types: • IU r-register 32-bit register which can be used for general purposes • IU Status/Control Register Used for IU status display and control •...
Page 28: Memory Mapped Registers
MB86860 Series Hardware Manual 3.2. Memory Mapped Registers These are registers located in memory address spaces. They are used for processor and system status display and control. The registers shown below can be accessed by the Load from Alternate Space (LDA) instruction and the Store into Alternate Space (STA) instruction.
Page 29 MB86860 Series Hardware Manual 0x04 0x80000840 SDRAM START Address Register0 SSAR0 SDRAM 0x04 0x80000848 SDRAM START Address Register1 SSAR1 SDRAM 0x04 0x80000850 SDRAM START Address Register2 SSAR2 SDRAM 0x04 0x80000858 SDRAM START Address Register3 SSAR3 SDRAM 0x04 0x80000860 SDRAM Address Mask Register0 SAMR0 SDRAM Address...
Page 30 MB86860 Series Hardware Manual 0x0c 0x00001000 ICache Tag Diagnostics set 1 ICTAG1 ICache 0x00001FE0 0x0c 0x00001000 ICache Tag Diagnostics set 2 ICTAG2 ICache 0x00001FE0 0x0c 0x00001000 ICache Tag Diagnostics set 3 ICTAG3 ICache 0x00001FE0 0x0d 0x00001000 ICache Data Diagnostics set 0 ICDATA0 ICache 0x00001FF8...
Page 31 MB86860 Series Hardware Manual Address Register Name Symbol Class 0x0d 0x00002000 ICache Data Diagnostics set 1 ICDATA1 ICache 0x00002FF8 0x0d 0x00003000 ICache Data Diagnostics set 2 ICDATA2 ICache 0x00003FF8 0x0d 0x00004000 ICache Data Diagnostics set 3 ICDATA3 ICache 0x00004FF8 0x1c 0x00000000 DCache Tag Diagnostics set 0 DCTAG0...
Page 32: Processor Core
MB86860 Series Hardware Manual 4. Processor Core 4.1. Summary The MB8686 Processor Core (called the MB8686x Core below) is a High-end embedded SPARC processor Core developed for installation on the basis of the HyperSPARC (RT6xx). The MB6868 Core is configured from the following function blocks: •...
Page 33 MB86860 Series Hardware Manual IADDR[32] DEBUG DADDR[32] SUPPORT UNIT IPATH instruction fetch, decode, dual issue and the scheduler units super scalar CDATA[64] CINST[64] LDSTDATA[64] 16KB 4 way 16KB 4 way D_CACHE I_CACHE PR_IMD[64] BIU + I/O MB8686x CORE IMA[32] IMD[64]...
Page 34: Iu (Integer Unit)
MB86860 Series Hardware Manual 4.2. IU (Integer Unit) 4.2.1. Summary Here a block diagram of the IU in the MB8686x Core is shown. The MB8686x processor Core uses super- scalar architecture, and it can both fetch 2 instructions at a time and issue 2 instructions at a time. Figure 4-2 MB8686x Core IU Block Diagram Data Load-store...
Page 35 MB86860 Series Hardware Manual – – Ancillary State Register 31 ASR31 00000000 00000000 00000000 00000000 (ICCR)
Page 36: Register Details
MB86860 Series Hardware Manual 4.2.3. Register Details 4.2.3.1. IU r-register Figure 4-3 IU r-register The IU Register is a 32-bit general purpose register. 4.2.3.2. Program Counter (PC) The PC indicates the instruction addresses fetched in the IU (Integer Unit). The PC fetches the contents of nPC at the end of each instruction.
Page 37 MB86860 Series Hardware Manual Symbol :nPC Reset State :0x4 4.2.3.4. Processor State Register (PSR) Register PS displays basic processor control and status. Register PS can be accessed by instruction RDPS (privileged instruction) and instruction WRPS (privileged instruction). In order to support the Little-endian function, the PSR.DE field has been added to the MB8686 processor.
Page 38 MB86860 Series Hardware Manual - Previous Supervisor Preserves the value of the PSR.S bit when traps occur. PS bit is written back to S bit by a return from a trap (RETT instruction)
Page 39 MB86860 Series Hardware Manual Field Name Description - Enable Traps Interrupt traps are enabled by writing “1” to this bit. 0: Interrupts prohibited (interrupt traps ignored) 1: Interrupts enabled - Current Window Pointer Pointer which indicates current active register window. The range which can be set in the MB8686x processors is bit0-7.
Page 40 MB86860 Series Hardware Manual TBA<31:12> zeros Symbol :WIM Reset State :undefined...
Page 41 MB86860 Series Hardware Manual Table 4-1 Field Name Description 31-12 - Trap Base Address Sets the upper order 20b of the trap table base address. 11-4 - trap type When traps occur, offset values are set to the trap tables corresponding to the traps.
Page 42 MB86860 Series Hardware Manual 4.2.3.8. DIAG register (ASR30) SIFD SDFD Reserved 01010001 Reserved Symbol :DIAG or ASR30 Reset State :0x80005100 Field Name Description - ALU TwoEnable Reset state: 1 - ICACHE Disable 0: ICache enable 1: ICache disable Reset state: 0 - DCache Disable 0: DCache enable 1: DCache disable...
Page 43 MB86860 Series Hardware Manual By executing Flush Instruction issued. 4-12...
Page 44 MB86860 Series Hardware Manual - CACHE Enable for both ICache and DCache Enables ICache and DCache 0: ICache/DCache disable 1: ICache/DCache enable Reset state: 0 Figure 4-11 Instruction Cache Control Register 4-13...
Page 45: Caches
MB86860 Series Hardware Manual 4.3. Caches 4.3.1. Summary MB8686 processors are equipped with instruction and data caches which are each 16Kbyte (4-way set associative), and the data caches use one-way type write through. 4.3.2. Cache Memory Assignments Table 4-3 Cache ASI Assignments Address Register Name Symbol...
Page 46: Tag/Data Format
MB86860 Series Hardware Manual DCache Data Diagnostics Set 0 DDATA0 0x00000FF8 0x1d 0x00000000 DCache Data Diagnostics Set 1 DDATA1 0x00000FF8 0x1d 0x00000000 DCache Data Diagnostics Set 2 DDATA2 0x00000FF8 0x1d 0x00000000 DCache Data Diagnostics Set 3 DDATA3 0x00000FF8 0x31 Flush Entire ICache/DCache 4.3.3.
Page 47: Operating Functions
MB86860 Series Hardware Manual 4.3.4. Operating Functions 4.3.4.1. Cache Control ASR30(DIAG) and ASR31(DIAG) registers (see 4.2.3.8 and 4.2.3.9) are used to control cache operations. The settings shown below are required to enable cache functions. It is also necessary to set DBU (Data Buffer Unit) fuctions for valid use of cache functions (see 6.
Page 48: Dsu (Debug Support Unit)
MB86860 Series Hardware Manual {Note} In Cache ON status there is no function for flushing DCache only. The method in (5) must be used on the assumption that ICache is also inenabled. 4.4. DSU (Debug Support Unit) 4.4.1. Summary The DSU (Debug Support Unit) is a hardware mechanism for supporting program debugging. The DSU function is valid when the value of BRKEN# sampled during a reset is “L”.
Page 49: Register Overview
MB86860 Series Hardware Manual 4.4.3. Register Overview Table 4-6 DSU Register Address Register Name Symbol Reset Value b24 b23 0x01 0x0000FF00 Instruction Address Descriptor Register1 IADR1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxx00 0x01 0x0000FF04 Instruction Address Descriptor Register2 IADR2 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxx00 0x01 0x0000FF18...
Page 50 MB86860 Series Hardware Manual - Break Go Reserved EIA2 - Enable Instruction Address 2 EIA1 - Enable Instruction Address 1 = Single Step Enable Reserved Figure 4-2 Debug Control Register 4.4.4.3. Debug Status Register (DSR) 16 15 12 11 Reserved TBPTR Reserved Reserved...
Page 51: Explanation Of Functions
MB86860 Series Hardware Manual 4.4.5. Explanation of Functions 4.4.5.1. Moving to Debug Mode There are 2 CPU modes: Normal Mode and Debug Mode . The EN_BRK bit of the DSR Register indicates the current mode: EN_BRK = 0 · · · Debug Mode EN_BRK = 1 ·...
Page 52 MB86860 Series Hardware Manual This break point is handled as a synchronous trap. The following are the 2 conditions for causing this trap: (1) Instruction Address Breaks The PC address matches 1 of ADR1/2, the PSR User / Supervisor bits match the US1/2 bits (DSR Register) which correspond to IADR, and the EIA1/2 bits of the DSR registers which correspond to these are set.
Page 53 MB86860 Series Hardware Manual pPS and pET are new bits for debug traps. These are assigned to bits 9 and 8 of the DSR Register and are Read Only bits. 4.4.5.5. BRKGO Output Pin The MB8686 has a BRKGO output pin. This always reflects the BG bit of the DCR Register. When this bit is “1”, it indicates that instruction fetches and data access are for debug trap routines.
Page 54 MB86860 Series Hardware Manual 4.4.5.6. Register Fields Handling of register fields in debug traps is the same as for normal traps, and the CWP is decremented. Handling of register fields in debug trap routines is left entirely to the software. 4.4.5.7.
Page 55: Low Power Consumption Mode
MB86860 Series Hardware Manual 4.5. Low Power Consumption Mode 4.5.1. Summary The MB8686 has 2 modes for low power consumption: Sleep Mode and Stop Mode. Sleep Mode The PLL keeps on operating, but the clocks which provide peripheral functions stop. Normal operation can continue after Sleep Mode is canceled.
Page 56 MB86860 Series Hardware Manual Figure 4-14 Sleep Mode Register 4-25...
Page 57: Explanation Of Functions
MB86860 Series Hardware Manual 4.5.5. Explanation of Functions Conversion to Low Power Consumption Mode must be done in Cache-Off status. In the MB8686 processor, cache-off status is called Cache-Off Mode, and operating status using caches is called Normal Mode. The following diagram shows MB8686 processor status conversions: Figure 4-15 Power Save State Diagram RESET# CACHE-OFF...
Page 58 MB86860 Series Hardware Manual [Note] When converting from Cache-Off Mode to Normal Mode, a cache flush (access to ASI0x31space) is required before setting the ICCR Register. 4-27...
Page 59: Items Requiring Attention In Sleep Mode
MB86860 Series Hardware Manual 4.5.6. Items Requiring Attention in Sleep Mode In the Sleep Function in the MB8686, at the point in time when it goes into Sleep Mode the processor becomes unable to receive BREQ# signals. Moreover, operation in which Sleep Mode entry timing and BREQ# signal assert timing conflict is not guaranteed.
Page 60: Tlb
MB86860 Series Hardware Manual 5. TLB 5.1. Summary This TLB converts virtual addresses to physical addresses in accordance with the address conversion table. However, no memory protection function causing traps to occur when there is a TLB-miss is supported. When the TLB function is not used, addresses from the CPU are output as they are as physical addresses.
Page 61: Register Overview
MB86860 Series Hardware Manual 5.6. Register Overview Table 5-1 TLB Registers Address Register Name Symbol Reset Value b23 b16 b15 b8 b7 0x04 0x80000008 TLB Control Register xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx 0x04 0x80001400 Virtual Word Address Entry Register00 VWE00 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx 0x04 0x80001408...
Page 62 MB86860 Series Hardware Manual 0x04 0x800014C0 Virtual Word Address Entry Register12 VWE12 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx 0x04 0x800014C8 Physical Word Address Entry Register12 PWE12 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx 0x04 0x800014D0 Virtual Word Address Entry Register13 VWE13 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx 0x04 0x800014D8 Physical Word Address Entry Register13...
Page 63: Register Details
MB86860 Series Hardware Manual 5.7. Register Details 5.7.1. TLB Control Register (TCR) Setting “1” to the TE bit of this register enables the Address Conversion Function. At least one batch of entries (VWE, PWE) must be set. When TE=“0”, addresses are output from the CPU as they are as physical addresses.
Page 64: Operating Functions
MB86860 Series Hardware Manual Reserved Symbol :PWE00-15 Address :0x800014008-0x800014F8 (ASI=0x4) Reset State :undefined Field Name Description 31-12 - Physical Page Number Sets upper order bits of the physical addresses corresponding to virtual addresses set in the corresponding VWEL registers. Page size is set by the PS bit. 11-5 Reserved - Page Size...
Page 65 MB86860 Series Hardware Manual 64MB page (PS=1111) PPN[31:26] VA[25:0] Figure 5-2 Physical Address...
Page 66 MB86860 Series Hardware Manual When the TE bit of the TCR is set to “0”, no TLB address conversions are performed, and virtual addresses go out as they are to the exterior as physical addresses. Also, if the Physical Word V bit is “0”, even if a VA hits in that entry, the VA becomes a physical address as is without being converted.
Page 67: Data Buffer Unit
MB86860 Series Hardware Manual 6. Data Buffer Unit 6.1. Summary The Data Buffer Unit consists of an Instuction Buffer (IB), Data Read Buffer (RB) and Write Buffer (WB). It is a module for the efficient performance of instruction and data transfers between the CPU and external memory starting with SDRAM based on burst access.
Page 68: Register Overview
MB86860 Series Hardware Manual 6.2. Register Overview Table 6-1 Data Buffer Registers Address Register Name Symbol Reset Value b23 b16 b15 b8 b7 0x04 0x80000000 Buffer Control Register 00000000 00000000 00000000 00000000 6.3. Register Details 6.3.1. Buffer Control Register (BCR) Register which performs all buffer controls and settings.
Page 69 MB86860 Series Hardware Manual - Instruction Buffer Enable Instruction Buffer is enabled by setting “1” to this bit. 0: Instruction Buffer Disable 1: Instruction Buffer Enable Reset state: 0...
Page 70: Buffer Control Register
MB86860 Series Hardware Manual - Read Buffer Enable Read Buffer is enabled by setting “1” to this bit. 0: Read Buffer Disable 1: Read Buffer Enable Reset state: 0 - Write Buffer Enable Write Buffer is enabled by writing “1” to this bit. 0: Write Buffer Disable 1: Write Buffer Enable Reset state: 0...
Page 71 MB86860 Series Hardware Manual immediately preceding data (hit in FIFO input column tag), it overwrites the valid locations. (When the merge function and Merge & Collapse are enabled).
Page 72: Buffer Link Policy
MB86860 Series Hardware Manual • Controls WB data with valid bits in byte units and reflects to the Byte Enable pin during output. • Handles atomic-load/store instructions as non-cache in all areas. 6.4.4. Buffering Policy • The IB and RB are accessed in accordance with the order of instruction execution. •...
Page 73: Tag Format
MB86860 Series Hardware Manual Figure 6-4 Access Order between RB and WB (continued) Access Type Burst Operation Judgment Access Cache Area Store IB: hit First writes WB, then writes data to external memory. Data Access ASI==8, 9 IB: miss Store RB: hit First writes WB, then writes data to external memory.
Page 74 MB86860 Series Hardware Manual S: Supervisor V: Valid bit Figure 6-6 Buffers Tag Format...
Page 75: Sparclite Bus Interface
MB86860 Series Hardware Manual 7. SPARClite Bus Interface 7.1. Summary The SPARClite Bus is the bus for connecting memory and I/O devices, and it operates synchronous to the bus clock (CLKIN). The SPARClite Bus Interface controls data transfers between the SPARClite Bus and the BIU Bus.
Page 76: Register Details
MB86860 Series Hardware Manual 7.3. Register Details 7.3.1. Address Range Specifier Registers (ARSR0–5) These are the registers for setting SPARClite Bus CS0#~CS5# address ranges. The start address of an address range is set to these registers. Bits which do not perform address comparisons are set in the AMR Registers.
Page 77: Wait State Specifier Registers (Wssr0-5)
MB86860 Series Hardware Manual Reserved ASI mask<5:0> Address mask<31:16> Symbol :AMR0–5 Address :0x80000200-0x80000228 (ASI=0x4) Reset State :undefined (AMR0=0x00030001) • • • • AMR0 (Address 0x80000200, ASI=0x4) for setting SPARC area CS0# (exclusively for ROM areas 0x00030001 on reset) • • • • AMR1 (Address 0x80000208, ASI=0x4) for setting SPARC area CS1# (undefined on reset) •...
Page 78 MB86860 Series Hardware Manual - count2 Specifies the number of waits for the 2nd cycle on of burst transfers. The specified value of this field + 1 is the number of waits. Thus, if 0 is specified, there is 1 wait. These bits are valid when [WE] is “1”.
Page 79: Mexc Parity Error Control Registers (Mxpef)
MB86860 Series Hardware Manual - wait enable Enable generation of internal waits for corresponding CS areas. [OVR], [CN1], [CN2] and [SCB] are all enabled when [WE] is “1”. Reserved -override When this bit is “1”, external READY# is also received. (Gives priority to READY# which comes first).
Page 80: Idle Cycle Control Register
MB86860 Series Hardware Manual Reserved MXWEE Symbol :MXPECR Address :0x80000438 (ASI=0x4) Reset State :0x00000000 Field Name Description 31-2 Reserved - Parity 0: Even parity 1: Odd parity MXWEE - MEXC Write Drive Enable 1: Write Error enable 2: Write Error disable Figure 3-9 MXPECR Register 7.3.6.
Page 81: Operating Functions
MB86860 Series Hardware Manual 7.4. Operating Functions 7.4.1. Operations when the CPU has the Bus Right The MB8686 has a 64-bit data bus, and bus width and cache/non-cache can be set CS (Chip Select) area by area. SPARClite bus cycles depend on read/write, cache/non-cache and bus width, and operations change in accordance with these.
Page 82 MB86860 Series Hardware Manual In 32-bit bus, burst length is 8, in 16-bit bus, burst length is 16 and in 8-bit bus it is 32. When burst transfers do not take place, the required number of single transfers is performed as shown in the above table.
Page 83 MB86860 Series Hardware Manual Reads from non-cache areas are handled as single transfers, and only BEx corresponding to the data requested by a CPU instruction are asserted. In 64-bit bus width the operation definitely ends in one bus cycle. In 32, 16 and 8-bit bus widths, the decision as to how many times single transfers are repeated depends on bus width and data type.
Page 84 MB86860 Series Hardware Manual 8bit 64bit 16bit 32bit 32bit 16bit 64bit 8bit 7-10...
Page 85 MB86860 Series Hardware Manual 7.4.1.5. Address Cycles In read cycle and write cycle changeovers, an address cycle of at least one clock cycle is inserted. In sequential reads and writes, there are times when an address cycle is not inserted. When the CPU accesses SDRAM and when read access makes a cache hit, CPU access to the SPARClite bus does not take place, and there is no upper limit regulation of idle cycles.
Page 86 MB86860 Series Hardware Manual The MB8686 has a MEXC# input pin for notifying the CPU of an abnormality when for whatever reason an exception occurs externally during access (for example, an area with no resources is accessed or there is absolutely no reply and a time out occurs).
Page 87 MB86860 Series Hardware Manual However, the method of communicating a MEXC# on the SPARClite bus to the CPU Core differs according to the access type as shown below: • Burst Read by Cache Misshit MEXC# If a MEXC# occurs during a burst transfer, the bus cycle continues without pause until the transfer is completed.
Page 88 MB86860 Series Hardware Manual • Reads If 1 is set to bit0 of the WSS, a Parity Check is performed. If a Parity Error then occurs, 1 is set to bit0 of the MXPEF as a flag, and this is transmitted to the CPU as a MEXC. By checking bit0 of the MXPEF with a trap routine, the user can confirm that a Parity Error occurred in a read.
Page 89 MB86860 Series Hardware Manual 7.4.1.12. SPARClite Bus Timing SPARClite Bus Cycle classifications when the CPU has the bus right are as shown below. Table 7-9 SPARClite Bus Cycle Classifications Bus Cycle Normal Operation MEXC# Reply to Bus Width Data Type Ending BREQ# Burst Read:...
Page 90 MB86860 Series Hardware Manual CLKIN Data Buffer Idle Data Non-Burst read cycle Write RDWR# AS<3:0> ADR<31:2 > D<63:0> BE0# • ` BE7# CSx# DTYP<1:0> READY# Figure 7-8 SPARClite Single Read/Write Operation 7-16...
Page 91 MB86860 Series Hardware Manual CLKIN Data Buffer/DMAC Idle Data Buffer/DMAC Idle Burst read cycle Burst read cycle (RD#) RDWR# BMREQ# BMACK# ASI[3:0] Not change Not change ADR[31:5] ADR[4:3] DATA[63:0] BE0#~BE7# 8’b0000000 8’b0000000 8’b0000000 8’b000000 8’b000000 CSx# DTYP[1:0] READY# Figure 7-9 SPARClite Bus Burst Read Operation 7-17...
Page 92 MB86860 Series Hardware Manual CLKIN DMAC Idle Data Buffer write Idle Burst write cycle (cache region) cycle (RD#) RDWR# BMREQ# BMACK# ASI[3:0] Not change Not change ADR[31:5] ADR[4:3] DATA[63:0] BE0#~BE7# 8’b0000000 8’b0000000 8’b0000000 8’b000000 8’b011010 CSx# DTYP[1:0] READY# Figure 7-10 SPARClite Bus Burst WRITE Operation 7-18...
Page 93: Access Transparent Mode To Sdram (Mb86861 Only)
MB86860 Series Hardware Manual 7.4.2. Access to SDRAM Transparent Mode (MB86861 only) During bus grant, the MB8686 supports a function whereby the external bus master on the SPARClite bus access SDRAM through the MB8686. Hereafter this function will be called Transparent Access Function, Transparent Access Mode or simply Transparent Mode, and transparent access to SDRAM will simply be called Transparent Access.
Page 94 MB86860 Series Hardware Manual asserted when data is fetched from the D<63:0> pin to a buffer. During writes, BE0#~7# are fetched at the same time as the data is fetched, and only bytes which correspond to BE# which are “L” are written to SDRAM.
Page 95 MB86860 Series Hardware Manual CLKIN Idle Single Read Cycle Cycle SDSEL# ASI<3:0> Don’t care ADR<31:3> RDWR# BLEN8# D<63:0> Invalid • ` BE0# BE7# Don’t care DTYP<1:0> Don’t care RDYOUT# BMREQ# Figure 7-12 Single Reads in SDRAM Transparent Access 7-21...
Page 96 MB86860 Series Hardware Manual CLKIN Single Write Idle Cycle Cycle SDSEL# ASI<3:0> Don't Care ADR<31:3 RDWR# BLEN8# D<63:0> • ` BE0# BE7# DTYP<1:0> Don't Care RDYOUT# BMREQ# Figure 7-13 Single Writes in SDRAM Transparent Access Translator’s Note: This is numbered Figure 7-5 in the Japanese text. Since there is already a Figure 7-5 on page 7-16, however, I have changed the number to read consecutively.
Page 97 MB86860 Series Hardware Manual CLKIN SDSEL# ADR<31:3> Don't Care RDWR# BLEN8# DATA<63:0> Invalid RDYOUT# BMREQ# BMACK# Figure 7-14 Burst Reads in SDRAM Transparent Access (Burst Length 8) 7-23...
Page 98 MB86860 Series Hardware Manual CLKIN SDSEL# ADR<31:3 Don't Care > RDWR# BLEN8# DATA<63:0> • ` BE0# RDYOUT# BMREQ# BMACK# Figure 7-15 Burst Writes in SDRAM Transparent Access (Burst Length 8) 7-24...
Page 99: Sdram-If
MB86860 Series Hardware Manual 8. SDRAM-IF 8.1. Summary The SDRAM-IF is a module attached to the Bus Interface Unit (BIU) which functions as an interface between the MB8686 Processor Core and external chip circuits, and it has the following functions: (1) Has dedicated 13-bit address and 64-bit data bus pins.
Page 100: Register Overview
MB86860 Series Hardware Manual 8.3. Register Overview Table 8-2 SDRAM-IF Registers Address Register Name Symbol Reset Value b24 b23 b16 b15 0x04 0x80000130 SDRAM Address Range Specifier Register0 SDARSR0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0x04 0x80000138 SDRAM Address Range Specifier Register1 SDARSR1 xxxxxxxx xxxxxxxx xxxxxxxx...
Page 101: Register Details
MB86860 Series Hardware Manual 8.4. Register Details 8.4.1. SDRAM Address Range Specifier Registers (SDARSR0–1) These are the registers for setting SDRAM bus areas. Address range start addresses are set to these registers. Bits not performing address comparisons are set in the SDAM Registrers. When the SDARSR.N bit is 1, its range is made a non-cache area.
Page 102: Sdram Configuration Register (Sdcfg)
MB86860 Series Hardware Manual 21-16 Sets SDRAM Area ASI masks. mask<5:0> 15-0 Address Sets SDRAM Area Address masks. mask<31:16> Figure 8-2 Address Mask Register 8.4.3. SDRAM Configuration Register (SDCFG) In order to enable SDRAM I/F functions, the SE bit of this register must be set to “1”. When an SDRAM which is connected to the MB8686 comes with register functions, Buffer Mode (BUF) should be enabled.
Page 103 MB86860 Series Hardware Manual Field Name Description 31-16 Reserved 15-0 - Timer Count Specifies issue space of the Auto Refresh (REF) command issued to SDRAM. × (ART.TC / ((input clock frequency) (clock frequency multiplier frequency)) (sec) is the REF command issue space. Figure 8-4 Auto Refresh Timer Register...
Page 104: Sdram Status Register (Ssr)
MB86860 Series Hardware Manual 8.4.5. SDRAM Status Register (SSR) This register indicates the status of the SDRAM I/F Unit. When the initial settings to SDRAM have been completed, 1’b1 is set to the SDI bit. This bit is Read Access Only. When parity errors occur in SDRAM data reads, 1’b1 is set to the PER bit.
Page 105 MB86860 Series Hardware Manual Field Name Description 31-17 Reserved 18-16 -RAS Precharge Time Sets SDRAM tRP (RAS Precharge Time) used in corresponding SDCS# areas. 000–001 : Reserved : 2 cycle : 3 cycle 100–111 : Reserved Reserved 14-12 tRCD - RAS-CAS Delay Time Sets SDRAM tRCD (RAS-CAS Delay Time) used in corresponding SDCS# areas.
Page 106: Sdram Start Address Registers (Ssar0-3) (Mb86861 Only)
MB86860 Series Hardware Manual 8.4.7. SDRAM Start Address Registers (SSAR0-3) (MB86861 only) This register is for setting SDRAM address areas which correspond to the SDCS. The upper order 16 bits of the start addresses of corresponding SCS areas should be set to the SSAR Register. Address range is decided by making settings grouped with the SAM register.
Page 107: Operating Functions
MB86860 Series Hardware Manual (0x00000000 on reset) Field Name Description 31-16 Reserved 15-0 Address Mask -SDRAM Address Mask<31:15> <31:15> Figure 8-8 SDRAM Address Mask Register 8.5. Operating Functions 8.5.1. Parity Generation and Check Function During read access to the relevant SCS the parity check function is enabled, and during write access the parity generation function is enabled by setting “1”...
Page 108 MB86860 Series Hardware Manual 8.5.2.3. SDRAM Parity All SDRAM Parity bits and SDRAM Data Correspondence are as shown below. Table 8-5 SDRAM Parity Bus Size <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> 64bit mode SDP0 SDP1 SDP2 SDP3 SDP4 SDP5 SDP6 SDP7...
Page 109 MB86860 Series Hardware Manual • SDRAM DIMM Block Diagram Example-1 RS#0 RDQMB0 RDQMB4 DQ32 I/O 0 I/O 0 S#0/S#2 RS#0/RS#2 DQ33 I/O 1 I/O 1 DQMB0 to DQMB7 RDQMB0 - RDQMB7 DQ34 I/O 2 I/O 2 • ¨ BA0-BA1 RBA0-RBA1 BA0-BA1:SDRAMS D0-D15 DQ35 I/O 3...
Page 110 MB86860 Series Hardware Manual SDRAM DIMM Block Diagram Example-2 S#0-S#3 RS#0-RS#3 DQMB0 to DQMB7 RDQMB0 - RDQMB7 BA0-BA1 RBA0-RBA1 • ¨ BA0-BA1:SDRAMS D0-D31 • ¨ A0-A11 RA0-RA11 A0-A11:SDRAMS D0-D31 RAS# RRAS# • ¨ RAS#:SDRAMS D0-D31 CAS# RCAS# • ¨ CAS#:SDRAMS D0-D31 RWE# •...
Page 111 MB86860 Series Hardware Manual • Example of SDRAM DIMM, shown in Fig 8-3 SDRAM DIMM Block Diagram Example-1, connections with the MB8686x. SS200 SDRAM I/F SDRAM DIMM(1) SDRAM DIMM(2) SDRAM DIMM(3) SDRAM DIMM(4) SCLK SCKE CKE0 CKE0 CKE0 CKE0 SRAS# RAS# RAS# RAS#...
Page 112 MB86860 Series Hardware Manual 8-14...
Page 113: Timing Diagram
MB86860 Series Hardware Manual 8.5.3. Timing Diagrams 8.5.3.1. Access Time SCLK tRAC SRAS# SCAS# tRCD tCAC (READ 64bit Bus) (READ 32bit Bus) (WRITE 64bit Bus) (WRITE 32bit Bus) CL= 3 Figure 8-9 Access Time 8.5.3.2. CAS Output Delay (1) Same Bank Access (read) SCLK lCCD 64bit Bus Mode...
Page 114 MB86860 Series Hardware Manual Same bank access (write) and mask by DQ Data mask control by DQ is performed only for write data to SDRAM SCLK lCCD 64bit Single Write Write Write SDQM 64bit Bus lCCD 64bit Burst Write Write Write 64bit Bus lCCD...
Page 115 MB86860 Series Hardware Manual 8.5.3.3. RAS Output Delay SCLK Bank0 Bank1 SADR ACTV Write ACTV Write tRRD tRAS 64bit Bus Figure 8-12 RAS-RAS Delay 8.5.3.4. Timing from Writes to Reads SCLK Write Read 64bit Bus 8.5.3.5. Initialize Operation The SDRAM I/F performs the following initialize operations for SDRAM after a Reset signal has been canceled: (1) Transmits a 200-cycle nop.
Page 116 MB86860 Series Hardware Manual SCLK RESET# REF Cycle for SCS0 REF Cycle for SCS1 tINI • ~ REF is asserted 8 times PALL REF0 REF1 PALL REF0 SCS0-3 SCS0 SCS0 SCS0 SCS1 SCS1 SCLK RESET# REF Cycle for SCS3 tRSC PALL REF7 ACTV...
Page 117 MB86860 Series Hardware Manual Programmers should use the following procedures to confirm the initial settings of the SDRAM to be used as well as the end of the initialize operation: (1) Use the SDRAM Start Address Registers (SSAR0-3) and the SDRAM Address Mask Registers (SAMR0- 3) to specify SDRAM CS area ranges to be used.
Page 118 MB86860 Series Hardware Manual 8.5.3.7. Registered Mode SDRAM DIMM ..bit12 Unregistered Registered When SDRAM DIMM is used in registered mode, CAS Latency(CL) of SDRAM is increased by 1cycle. SDRAM Ctlr. of the MB86860 aloso behaves in the way. 1. Read Sequence <Unregistered Mode, CL=2>...
Page 119 MB86860 Series Hardware Manual <Registered Mode, CL=2> On the Registered SDRAM DIMM, Control Signals, which are CS,BA,ADR,RAS,CAS,WE and DQM, are delayed with 1 cycle and Data Output from SDRAM DIMM is also delayed with 1 cycle. CLKIN RAS# CAS# DATA CL+1 tRCD 8-21...
Page 120 MB86860 Series Hardware Manual 2. Write Sequence <Write Operation on Unregistered Mode> CLKIN RAS# CAS# DATA M1 M2 tRCD On the Registered SDRAM DIMM, Control Signals, which are CS,BA,ADR,RAS,CAS,WE and DQM, are delayed with 1 cycle and Data Input to SDRAM DIMM also needs to be delayed with 1 cycle.
Page 121 MB86860 Series Hardware Manual CLKIN RAS# CAS# DATA M0 M1 M2 TRCD+1 tRCD REGE Signal REGE(Register Enable) is a control signal of SDRAM DIMM itself and is not a signal from MB86860. When REGE signal is active High, it needs to be High level on the user's system. It is the specification of SDRAM DIMM.
Page 122 MB86860 Series Hardware Manual 8.5.3.7. Values Predetermined by Number of SDRAM I/F Cycles Table 8-7 Values Predetermined by Number of SDRAM I/F Cycles Parameter Symbol unit notes RAS# Access Time tRAC cycle RAS#-CAS# Delay Time tRCD cycle CAS# Access Time tCAC cycle CAS# to CAS# Delay...
Page 123: Dmac
MB86860 Series Hardware Manual 9. DMAC 9.1. Summary The DMAC supports flow-through transfers between SPARClite buses and SDRAM buses. All set registers have 2 channels. Simultaneous operation is 1 channel only. The DMAC cannot be used when Transparent Access Mode is in use. •...
Page 124: Dma Source Address Register
MB86860 Series Hardware Manual DBWn bit specifies the destinatioin data bus width. The TCn bit controls EOP signals. When this signal is set to “1”, an EOP signal is output at the end of a transfer. The SBn bit controls DMA operations. If this bit is set to “1”, DMA operation starts.
Page 125 MB86860 Series Hardware Manual • • • Address : 0x80000C28 (ASI=0x4) DMSAR1 Reset State : 0x00000000 Field Name Description 31-5 - Source Address Sets the upper order 27 bits of the transfer source address. Reserved - ASI Sets ASI of transfer source area. Figure 9-2 DMSAR Register...
Page 126: Dma Destination Address Register
MB86860 Series Hardware Manual 9.4.3. DMA Destination Address Registers DMA Destination Address Registers are used to specify destination addresses of DMA transfers. These registers are assigned to 0x80000c10 (DMDA0 for channel0) and 0x80000c30 (DMDA1 for channel1). The setting unit is burst length (32 bytes). Transfer destination ASI are specified by the lower order 4 bits. •...
Page 127 MB86860 Series Hardware Manual The DMAC is connected to the internal chip BIU bus. The CPU Core has priority for the BIU bus right. DMA transfers are activated by setting activation bit SB of the DMA Control Registers (DMCR0, 1) to 1. If a CPU Core access request occurs in a DMA operation, DMA opens a bus right in burst transfer units and, once the CPU has opened a bus right, continues to operate.
Page 128: Transfer System
MB86860 Series Hardware Manual 9.5.2. Transfer System The DMAC has a 64-bit 4-column FIFO, and its basic bus cycle is a burst transfer of transfer length 4 (bus width 8 bytes 4 times = 32 bytes). It reads 4 transfer data sequentially in burst length from the memory spaces indicating source addresses and outputs the 4 data sequentially in burst length to the memory spaces indicating destination addresses.
Page 129 MB86860 Series Hardware Manual...
Page 130 MB86860 Series Hardware Manual 9.5.6. Block Diagram Figure 9-5 MB8686x DMA Block Diagram data address DMAC source address destination address CH0 Registers l‚ … Control Module Data FIFO CH1 Registers BIU bus...

Fujitsu SPARClite MB86860 Series User Manual

Quick Links

Need help?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Fujitsu SPARClite MB86860 Series

Summary of Contents for Fujitsu SPARClite MB86860 Series

Table of Contents