Primary Ide Connector Requirements; Figure 89. Connection Requirements For Primary Ide Connector - Intel Pentium 4 Design Manual

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9.1.3

Primary IDE Connector Requirements

The 10 kΩ resistor to ground on the PDIAG/CBLID signal is now required on both the Primary
and Secondary Connectors. This change is to prevent the GPI pin from floating if a device is not
present on either IDE interface.

Figure 89. Connection Requirements for Primary IDE Connector

* Due to ringing, PCIRST# m ust be buffered.
• 22 Ω – 47 Ω series resistors are required on RESET#. The correct value should be determined
for each unique motherboard design, based on signal quality.
• An 8.2 kΩ to 10 kΩ pull-up resistor is required on IRQ14 and IRQ15 to VCC3_3.
• A 4.7 kΩ pull-up resistor to VCC3_3 is required on PIORDY and SIORDY.
• Series resistors can be placed on the control and data line to improve signal quality. The
resistors are place as close to the connector as possible. Values are determined for each
unique motherboard design.
® ®
Intel Pentium 4 Processor / Intel
PCIRST# *
ICH2
3.3 V
4.7 k Ω
PIORDY (PRDSTB / PW DMARDY#)
IRQ 14
GPIOx
10 k
®
850 Chipset Family Platform Design Guide
PDD[15:0]
PDA[2:0]
PDCS[3,1]#
PDIOR#
PDIOW #
PDDREQ
PDDACK#
PDIAG / CBLID
Ω
I/O Controller Hub 2
3.3 V
8.2–10 k Ω
CSEL
IDE_primary_conn_require
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