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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
10.2.5 Timer D control registers
(1) Timer mode control registers D0 to D3 (TMCD0 to TMCD3)
The TMCDn registers control the operation of timer Dn (n = 0 to 3).
These registers can be read or written in 8-bit or 1-bit units.
Caution The TMDCAEn and other bits cannot be set at the same time. The other bits and the
registers of the other TMDn units should always be set after the TMDCAEn bit has been set.
7
6
TMCD0
0
CS02
TMCD1
0
CS12
TMCD2
0
CS22
TMCD3
0
CS32
Bit position
Bit name
6 to 4
CSn2 to CSn0
(n = 0 to 3)
1
TMDCEn
(n = 0 to 3)
5
4
3
CS01
CS00
0
CS11
CS10
0
CS21
CS20
0
CS31
CS30
0
Count Enable Select
Selects the TMDn internal count clock cycle (n = 0 to 3).
CSn2
CSn1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Caution The CSn2 to CSn0 bits must not be changed during timer
operation. If they are to be changed, they must be changed after
setting the TMDCEn bit to 0. If these bits are overwritten during
timer operation, operation cannot be guaranteed.
Remark f
: Internal system clock
XX
Count Enable
Controls the operation of TMDn (n = 0 to 3).
0: Count disabled (stops at 0000H and does not operate)
1: Counting operation is performed
Caution The TMDCEn bit is not cleared even if a match is detected by the
compare operation. To stop the count operation, clear the TMDCEn
bit.
User's Manual U14359EJ4V0UM
2
<1>
<0>
0
TMDCE0
TMDCAE0
0
TMDCE1
TMDCAE1
0
TMDCE2
TMDCAE2
0
TMDCE3
TMDCAE3
Function
CSn0
Count cycle
0
f
/4
XX
1
f
/8
XX
0
f
/16
XX
1
f
/32
XX
0
f
/64
XX
1
f
/128
XX
0
f
/256
XX
1
f
/512
XX
(1/2)
Address
After reset
FFFFF544H
00H
FFFFF554H
00H
FFFFF564H
00H
FFFFF574H
00H
353
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