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(2) EDO DRAM (when read, three idle states inserted)
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
WAIT (input)
Notes 1.
TRPW is always inserted for 1 or more cycles.
2.
This timing applies when in the RAS hold mode.
3.
This idle state (TI) is inserted by means of a BCC register setting. The number of idle states (TI)
to be inserted depends on the timing of bus hold request acknowledgement.
4.
This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
4. Timing from DRAM access to bus hold state.
132
CHAPTER 4
BUS CONTROL FUNCTION
Note 1
TRPW
T1
T2
Row
Column
address
address
indicates the sampling timing.
User's Manual U14359EJ4V0UM
Note 3
TE
TI
TH
Note 2
Data
Note 4
TH
TI
Undefined
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