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13.1 Features
• PWMn: 2 channels
• PWMn: Output pulse active level can be selected
• Operation clock can be selected from among f
clock)
• PWMn output resolution can be selected from among 8, 9, 10, 12 bits
Remark
n = 0, 1
13.2 Block Diagram
f
/2
XX
f
/4
XX
f
/8
selclk
XX
Selector
f
/16
XX
f
/32
XX
f
/64
XX
3
Note Reset has priority.
Remarks 1. n = 0, 1
2. f
: Internal system clock
XX
CHAPTER 13 PWM UNIT
/2, f
XX
0 to 7
0 to 8
Counter (TMPn)
(Edge latch)
0 to 9
0 to 11
12
0 to 7
0 to 8
Comparator
0 to 9
0 to 11
12
Compare register
(CMPn)
(Level latch)
Reload processing
12
PWM buffer register
2
(PWMBn)
(Level latch)
Preliminary User's Manual U14359EJ4V0UM00
/4, f
/8, f
/16, f
/32, f
XX
XX
XX
XX
Output control block
S
Q
Note
R
Match
Overflow
2
PWM control register n
(PWMCn) (Edge latch)
PWMCAEn
ALVn
PRMn1
PRMn0
0
/64 (f
is the internal system
XX
XX
PWMn
PWPn2
PWPn1
PWPn0
441
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