NEC V850E/MA1 User Manual page 163

CHAPTER 5
Bit position Bit name
11, 10 RHC1n, Row Address Hold Wait Control
RHC0n Specifies the number of wait states inserted as row address hold time.
(n = 1, 3,
4, 6)
9, 8 DAC1n, Data Access Programmable Wait Control
DAC0n Specifies the number of wait states inserted as data access time during DRAM access.
(n = 1, 3,
4, 6)
7, 6 CPC1n, Column Address Pre-charge Control
CPC0n Specifies the number of wait states inserted as column address precharge time.
(n = 1, 3,
4, 6)
4 RHDn RAS Hold Disable
(n = 1, 3, Sets the RAS hold mode.
4, 6) If access to DRAM during on-page operation is not continuous and another space is
accessed midway, the RASn signal is maintained in the active state (low level) during the
time the other space is being accessed in the RAS hold mode. In this way, if access
continues in the same DRAM row address following access of the other space, on-page
operation can be continued.
MEMORY ACCESS CONTROL FUNCTION
RHC1n RHC0n
0 0 0
0 1 1
1 0 2
1 1 3
DAC1n DAC0n
0 0 0
0 1 1
1 0 2
1 1 3
CPC1n CPC0n
0 0 0 (at least 1 wait is always inserted during on-page write access)
0 1 1
1 0 2
1 1 3
0: RAS hold mode enabled
1: RAS hold mode disabled
User's Manual U14359EJ4V0UM
Function
Number of wait states inserted
Number of wait states inserted
Number of wait states inserted
(2/3)
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