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11.2.2 Configuration
UARTn is controlled by the asynchronous serial interface mode register (ASIMn), asynchronous serial interface
status register (ASISn), and asynchronous serial interface transmission status register (ASIFn) (n = 0 to 2). Receive
data is held in the receive buffer (RXBn), and transmit data is written to the transmit buffer (TXBn).
Figure 11-1 shows the configuration of the asynchronous serial interface.
(1) Asynchronous serial interface mode registers 0 to 2 (ASIM0 to ASIM2)
The ASIMn register is an 8-bit register for specifying the operation of the asynchronous serial interface.
(2) Asynchronous serial interface status registers 0 to 2 (ASIS0 to ASIS2)
The ASISn register consists of a set of flags that indicate the error contents when a reception error occurs.
The various reception error flags are set (1) when a reception error occurs and are reset (0) when the ASISn
register is read.
(3) Asynchronous serial interface transmission status registers 0 to 2 (ASIF0 to ASIF2)
The ASIFn register is an 8-bit register that indicates the status when a transmit operation is performed.
This register consists of a transmit buffer data flag, which indicates the hold status of TXBn data, and the
transmit shift register data flag, which indicates whether transmission is in progress.
(4) Reception control parity check
Receive operations are controlled according to the contents set in the ASIMn register. A check for parity
errors is also performed during a receive operation, and if an error is detected, the value corresponding to the
error contents is set in the ASISn register.
(5) Receive shift register
This is a shift register that converts the serial data that was input to the RXDn pin to parallel data. One byte
of data is received, and if a stop bit is detected, the receive data is transferred to the receive buffer.
This register cannot be directly manipulated.
(6) Receive buffer (RXBn)
RXBn is an 8-bit buffer register for holding receive data. When 7 characters are received, 0 is stored in the
MSB.
During a reception enabled state, receive data is transferred from the receive shift register to the receive
buffer, in synchronization with the end of the shift-in processing of one frame.
Also, the reception completion interrupt request (INTSRn) is generated by the transfer of data to the receive
buffer.
(7) Transmit shift register
This is a shift register that converts the parallel data that was transferred from the transmit buffer to serial
data.
When one byte of data is transferred from the transmit buffer, the shift register data is output from the TXDn
pin.
This register cannot be directly manipulated.
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CHAPTER 11 SERIAL INTERFACE FUNCTION
User's Manual U14359EJ4V0UM
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