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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(4) Compare operation
The TMCn register has two capture/compare registers. These are the CCCn0 register and the CCCn1
register. A capture operation or a compare operation is performed according to the settings of both the
CMSn1 and CMSn0 bits of the TMCCn1 register. If the CMSn1 and CMSn0 bits of the TMCCn1 register are
set to 1, the register operates as a compare register.
A compare operation that compares the value that was set in the compare register and the TMCn count value
is performed.
If the TMCn count value matches the value of the compare register, which had been set in advance, a match
signal is sent to the output controller. The match signal causes the timer output pin (TO0n) to change and an
interrupt request signal (INTM0n0 or INTM0n1) to be generated at the same time.
If the CCCn0 or CCCn1 registers are set to 0000H, the 0000H after the TMCn register counts up from FFFFH
to 0000H is judged as a match. In this case, the TMCn register value is cleared (0) at the next count timing,
however, this 0000H is not judged as a match. Also, the 0000H when the TMCn register begins counting is
not judged as a match.
If match clearing is enabled (CCLRn bit = 1) for the CCCn0 register, the TMCn register is cleared when a
match with the TMCn register occurs during a compare operation.
Remark
n = 0 to 3
Count-up
TMC0
Compare register
(CCC00)
Match detection
(INTM000)
Remarks 1. The match is detected immediately after the count-up, and the match detection signal is
generated.
2. n ≠ 0000H
338
Figure 10-5. Compare Operation Example (1/2)
(a) When CCLR0 = 1 and CCC00 is other than 0000H
−
n
1
User's Manual U14359EJ4V0UM
n
n
0000H
0001H
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