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The CPU of the V850E/MA1 is based on RISC architecture and executes almost all the instructions in one clock
cycle using 5-stage pipeline control.
3.1 Features
• Minimum instruction cycle: 20 ns (@ 50 MHz internal operation)
• Memory space
Program space: 64 MB linear
Data space:
• Thirty-two 32-bit general-purpose registers
• Internal 32-bit architecture
• Five-stage pipeline control
• Multiply/divide instructions
• Saturated operation instructions
• One-clock 32-bit shift instruction
• Long/short instruction format
• Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
CHAPTER 3 CPU FUNCTION
4 GB linear
User's Manual U14359EJ4V0UM
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