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(b) When the data bus width is 8 bits (little endian) (1/2)
<1> Access to address (4n)
1st access
31
24
23
16
15
Address
8
7
7
4n
0
0
Word data
External
data bus
<2> Access to address (4n + 1)
1st access
31
24
23
16
15
Address
8
7
7
4n + 1
0
0
Word data
External
data bus
CHAPTER 4
BUS CONTROL FUNCTION
2nd access
31
24
23
16
15
Address
8
7
7
4n + 1
0
0
Word data
External
data bus
2nd access
31
24
23
16
15
Address
8
7
7
4n + 2
0
0
Word data
External
data bus
User's Manual U14359EJ4V0UM
3rd access
31
24
23
16
15
Address
8
7
7
4n + 2
0
0
Word data
External
data bus
3rd access
31
24
23
16
15
Address
8
7
7
4n + 3
0
0
Word data
External
data bus
4th access
31
24
23
16
15
Address
8
7
7
4n + 3
0
0
Word data
External
data bus
4th access
31
24
23
16
15
Address
8
7
7
4n + 4
0
0
Word data
External
data bus
113
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