NEC V850E/MA1 User Manual page 367

(4) Receive buffer registers 0 to 2 (RXB0 to RXB2)
These are 8-bit buffer registers for storing parallel data that had been converted by the receive shift register.
When reception is enabled (RXEn = 1 in the ASIMn register), receive data is transferred from the receive shift
register to the receive buffer, in synchronization with the completion of the shift-in processing of one frame.
Also, a reception completion interrupt request (INTSRn) is generated by the transfer to the receive buffer.
For information about the timing for generating these interrupt requests, see 11.2.5 (4) Receive operation.
If reception is disabled (RXEn = 0 in the ASIMn register), the contents of the receive buffer are retained, and
no processing is performed for transferring data to the receive buffer even when the shift-in processing of one
frame is completed. Also, no reception completion interrupt is generated.
When 7 bits is specified for the data length, bits 6 to 0 of the RXBn register are transferred for the receive
data and the MSB (bit 7) is always 0. However, if an overrun error occurs, the receive data at that time is not
transferred to the RXBn register.
Except when a reset is input, the RXBn register becomes FFH even when UARTCAEn = 0 in the ASIMn
register.
These registers are read-only in 8-bit units.
Remark n = 0 to 2
7 6
RXB0 RXB07 RXB06
RXB1 RXB17 RXB16
RXB2 RXB27 RXB26
Bit position Bit name
7 to 0 RXBn7 to
RXBn0
(n = 0 to 2)
CHAPTER 11 SERIAL INTERFACE FUNCTION
5 4 3
RXB05 RXB04 RXB03
RXB15 RXB14 RXB13
RXB25 RXB24 RXB23
Receive Buffer
Stores receive data.
0 can be read for RXBn7 when 7-bit character data is received.
User's Manual U14359EJ4V0UM
2 1 0
RXB02 RXB01 RXB00
RXB12 RXB11 RXB10
RXB22 RXB21 RXB20
Function
Address After reset
FFFFFA02H FFH
FFFFFA12H FFH
FFFFFA22H FFH
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