NEC V850E/MA1 User Manual page 133

(3) EDO DRAM (when written)
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
WAIT (input)
Notes 1. TRPW is always inserted for 1 or more cycles.
2. This timing applies when in the RAS hold mode.
3. This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
4. Timing from DRAM access to bus hold state.
CHAPTER 4 BUS CONTROL FUNCTION
Note 1
TRPW T1
Row
address
Data
indicates the sampling timing.
User's Manual U14359EJ4V0UM
T2 TE TH
Column
address
Note 2
Note 3
TH TI
Undefined
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