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Figure 6-11. Timing of 2-Cycle DMA Transfer (SRAM → → → → EDO DRAM) (3/3)
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Address (output)
BCYST (output)
CSn (output) of
SRAM area
RASm (output) of
DRAM area
CSn (output) of
other area
LCAS (output)
UCAS (output)
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Notes 1.
This idle state (TI) is independent of the BCC register setting.
2.
TRPW and TCPW are always inserted for one or more cycles.
3.
When a bus cycle accessing another CS space or a read cycle accessing the same CS space
follows this write cycle.
4.
In the case of the RAS hold mode
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
4. Col.: Column address
Row: Row address
234
CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
(c) Block transfer mode
T1
T2
T1
T2
T1
T2
TI
TI
TI
TI
TO
T1R
T2R
Address
Data
Data
Data
indicates the sampling timing.
User's Manual U14359EJ4V0UM
Note 2
TRPW
T1
T2
T1
T2
Note 1
TI
T1W T2W T2W
TE
T1R
T2R
Row
Col.
Address
Note 4
Data
Data
Note 2
TCPW
TB
Note 1
TI
T1W
T2W
TE
Col.
Note 3
Data
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