NEC V850E/MA1 User Manual page 185

(b) During off-page access (when latency = 2, page change)
SDCLK (output)
Command
BCYST (output)
SDCKE (output)
CSn (output)
SDRAS (output)
SDCAS (output)
WE (output)
LDQM (output)
UDQM (output)
Note (output)
Bank address (output)
A10 (output)
A0 to A9 (output)
D0 to D15 (I/O)
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
Figure 5-14. SDRAM Single Read Cycle (2/3)
TW TPREC
PRE
H
Address
Bank
Address
address
Address
Row
Address
address
indicates the sampling timing.
User's Manual U14359EJ4V0UM
Off-page
TACT TREAD TLATE TLATE
ACT RD
Address
Bank
Address
address
Row
Address
address
Row
Column address
address
Data
185