NEC V850E/MA1 User Manual page 557

Mnemonic Operand
OR reg1, reg2 r r r r r 0 0 1 0 0 0 R R R R R
ORI imm16, reg1, reg2 r r r r r 1 1 0 1 0 0 R R R R R
i i i i i i i i i i i i i i i i
PREPARE list12, imm5 0 0 0 0 0 1 1 1 1 0 i i i i i L
LLLLLLLLLLL00001
list12, imm5, 0 0 0 0 0 1 1 1 1 0 i i i i i L
Note 15
sp/imm L L L L L L L L L L L f f 0 1 1
imm16/imm32
RETI 0000011111100000
0000000101000000
SAR reg1, reg2 r r r r r 1 1 1 1 1 1 R R R R R
0000000010100000
imm5, reg2 r r r r r 0 1 0 1 0 1 i i i i i
SASF cccc, reg2 r r r r r 1 1 1 1 1 1 0 c c c c
0000001000000000
SATADD reg1, reg2 r r r r r 0 0 0 1 1 0 R R R R R
imm5, reg2 r r r r r 0 1 0 0 0 1 i i i i i
SATSUB reg1, reg2 r r r r r 0 0 0 1 0 1 R R R R R
SATSUBI imm16, reg1, reg2 r r r r r 1 1 0 0 1 1 R R R R R
i i i i i i i i i i i i i i i i
SATSUBR reg1, reg2 r r r r r 0 0 0 1 0 0 R R R R R
SETF cccc, reg2 r r r r r 1 1 1 1 1 1 0 c c c c
0000000000000000
APPENDIX B INSTRUCTION SET LIST
Opcode
GR[reg2]←GR[reg2]OR GR[reg1]
GR[reg2]←GR[reg1]OR zero-extend (imm16)
Store-memory (sp–4, GR[reg in list12], Word)
sp←sp–4
repeat 1 step above until all regs in list12 is stored
sp←sp-zero-extend (imm5)
Store-memory (sp–4, GR[reg in list12], Word)
GR[reg in list12]←Load memory (sp, Word)
sp←sp–4
repeat 2 steps above until all regs in list12 is loaded
Note 16
PC←GR[reg1]
if PSW.EP=1
←EIPC
then PC
PSW ←EIPSW
else if PSW.NP=1
then PC
PSW ←FEPSW
else PC
PSW ←EIPSW
GR[reg2]←GR[reg2] arithmetically shift right
GR[reg2]←GR[reg2] arithmetically shift right
if conditions are satisfied
then GR[reg2]←(GR[reg2] Logically shift left by 1)
OR 00000001H
else GR[reg2]←(GR[reg2] Logically shift left by 1)
OR 00000000H
GR[reg2]←saturated (GR[reg2]+GR[reg1])
GR[reg2]←saturated (GR[reg2]+sign-extend (imm5)
GR[reg2]←saturated (GR[reg2]–GR[reg1])
GR[reg2]←saturated (GR[reg1]–sign-extend (imm16)
GR[reg2]←saturated (GR[reg1]–GR[reg2])
If conditions are satisfied
then GR[reg2]←00000001H
else GR[reg2]←00000000H
User's Manual U14359EJ4V0UM
Operation
←FEPC
←EIPC
by GR[reg1]
by zero-extend (imm5)
(4/6)
Execution Flags
Clock
i r l CY OV S Z SAT
× ×
1 1 1 0
× ×
1 1 1 0
n+1 n+1 n+1
Note 4 Note 4 Note 4
n+2 n+2 n+2
Note 4 Note 4 Note 4
Note 17 Note 17 Note 17
4 4 4 R R R R R
× × ×
1 1 1 0
× × ×
1 1 1 0
1 1 1
× × × × ×
1 1 1
× × × × ×
1 1 1
× × × × ×
1 1 1
× × × × ×
1 1 1
× × × × ×
1 1 1
1 1 1
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