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(3) Bus cycle period control register (BCP)
In the V850E/MA1, the bus cycle period can be doubled during SRAM, external ROM, and external I/O
access. The bus cycle period is controlled using the BCP register. When the BCP bit of the BCP register is
set to 1, the external bus operates at one half the frequency of the internal system clock.
The clock can be output from the BUSCLK pin only in the bus cycle if the external bus cycle period is set to
two times that of the normal. Specify the bus cycle period as "Double" with the BCP register, then set the port
CM mode control register (PMCCM) and port CM function control register (PFCCM).
This register can be read/written in 8-bit units.
Cautions 1. During a flyby DMA transfer for SRAM, external ROM, or external I/O, the IORD and
IOWR signals are always output, irrespective of the IOEN bit setting.
In page ROM and EDO DRAM cycles, on the other hand, the IOEN bit setting has no
meaning.
2. Write to the BCP register after reset, and then do not change the set values.
3. If the CLKOUT output mode is selected for the PCM1 pin by using the PMCCM register
when the bus cycle period is doubled (BCP = 1), the bus cycle is half the frequency of
the internal system clock, but the same frequency as the internal system clock is output
from the PCM1 pin.
4. The BUSCLK signal is asserted active only when the external memory is accessed.
Otherwise, it is kept low.
7
6
BCP
BCP
0
Bit position
Bit name
7
BCP
3
IOEN
122
CHAPTER 4
BUS CONTROL FUNCTION
5
4
3
0
0
IOEN
Bus Cycle Period
Specifies the length of the bus cycle period.
BCP
0
Normal
1
Double
IORD, IOWR Enable
Specifies whether to enable/disable the operation of IORD and IOWR in SRAM, external
ROM, and external I/O cycles.
IOEN
0
Disables the operation of IORD and IOWR in SRAM, external ROM,
and external I/O cycles.
1
Enables the operation of IORD and IOWR in SRAM, external ROM,
and external I/O cycles.
User's Manual U14359EJ4V0UM
2
1
0
0
0
0
Function
Bus cycle period
Enable/disable IORD and IOWR operation
Address
After reset
FFFFF48CH
00H
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