Table of Contents
Advertisement
5.3.5 DRAM access
CLKOUT (output)
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
WAIT (input)
Notes 1.
TRPW is always inserted for 1 or more cycles.
2.
When a bus cycle accessing another CS space or a write cycle accessing the same CS space
follows this read cycle.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
CHAPTER 5
MEMORY ACCESS CONTROL FUNCTION
Figure 5-8. EDO DRAM Access Timing (1/5)
(a) Read timing (when no waits are inserted)
Note 1
TRPW
T1
Row address
indicates the sampling timing.
User's Manual U14359EJ4V0UM
T2
TB
TB
Column address Column address Column address
Data
Data
TE
Note 2
Data
165
Advertisement
Table of Contents
