NEC V850E/MA1 User Manual page 245

Figure 6-16. Timing of Flyby Transfer (DRAM → → → → External I/O) (1/3)
TI
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
A0 to A25 (output)
D0 to D15 (I/O)
RASm (output) of
DRAM area
CSn (output) of
H
external I/O area
BCYST (output)
H
RD (output)
OE (output)
H
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
H
IORD (output)
IOWR (output)
WAIT (input)
Note TRPW is always inserted for one or more cycles.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 (n ≠ m)
4. Col.: Column address
Row: Row address
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
(a) Block transfer mode
Note
TRPW
TI TI TI TO T1FH
indicates the sampling timing.
User's Manual U14359EJ4V0UM
T1 T2 TB
T2FH T1FH TF TE T1FH
Row
Col.
Data
TW
T1FH TF TE
Col.
Data
245