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<7>
<6>
PWMCn
PWMEn
ALVn
Bit position
Bit name
Note
PWMEn
7
(n = 0, 1)
6
ALVn
(n = 0, 1)
5, 4
PRMn1,
PRMn0
(n = 0, 1)
2 to 0
PWPn2 to
PWPn0
(n = 0, 1)
Note If PWMEn is changed from 0 to 1, the counter (TMPn) is reset to start counting from 000H (in 12 bits).
The first overflow permits the PWMn signal activation. If the bit length and operating clock of PWM0
and PWM1 are the same, the activation timing of these two PWMn signals can be adjusted. If PWMEn
was already 1, the counter is not reset upon an additional write of 1. When setting PWMEn to 1, set it
to 0 beforehand.
Remarks 1. n = 0, 1
2. f
: Internal system clock
XX
CHAPTER 13 PWM UNIT
5
4
3
PRMn1
PRMn0
0
PWM Enable
This bit is used to enable or disable PWMn operation.
0: PWM operation disabled
1: PWM operation enabled
Active Level
This bit is used to specify the active level for PWMn output.
0: Active level is low level
1: Active level is high level
The PWMn outputs inactive level (low level) of the ALVn bit after reset.
Prescaler Mode
This bit is used to select the bit length for the counter (TMPn) and compare register (CMPn).
PRMn1
PRMn0
0
0
0
1
1
0
1
1
PWM Prescaler Clock Mode
This bit is used to select the PWMn's operating clock.
PWPn2
PWPn1
PWPn0
0
0
0
0
0
1
0
1
1
0
1
0
Other than above
User's Manual U14359EJ4V0UM
2
1
0
PWPn2
PWPn1
PWPn0
Description
Bit length for TMPn and CMPn
8 bits
9 bits
10 bits
12 bits
Operating clock
0
f
/2
XX
1
f
/4
XX
0
f
/8
XX
1
f
/16
XX
0
f
/32
XX
1
f
/64
XX
Setting prohibited
Address
After Reset
FFFFFC00H,
40H
FFFFFC10H
443
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