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9.3.2 PLL mode
In PLL mode, an external resonator is connected or an external clock is input and multiplied by the PLL
synthesizer. The multiplied PLL output is divided by the division ratio specified by the clock control register (CKC) to
generate a system clock that is 10, 5, 2.5, or 1 times the frequency of the external resonator or external clock (f
After reset, an internal system clock (f
generated.
When a frequency that is 10 times the input clock frequency (f
low power consumption can be realized because a frequency of up to 50 MHz is obtained based on a 5 MHz external
resonator or external clock.
In PLL mode, if the clock supply from an external resonator or external clock source stops, operation of the internal
system clock (f
) based on the free-running frequency of the clock generator's internal voltage controlled oscillator
XX
(VCO) continues. However, do not devise an application method expecting to use this free-running frequency.
Example: Clock when PLL mode (f
System Clock Frequency (f
50.000 MHz
40.000 MHz
Caution When in PLL mode, only an f
clock maximum frequency (50 MHz) can be used for the oscillation frequency or external clock
frequency.
However, if any of 5 × × × × f
Remark If the V850E/MA1 does not need to be operated at high frequency, when PLL mode is selected a
power consumption can be reduced by lowering the system clock frequency using software (f
= 2.5 × f
f
, f
X
XX
9.3.3 Peripheral command register (PHCMD)
This is an 8-bit register that is used to set protection for writing to registers that can significantly affect the system
so that the application system is not halted unexpectedly due to an inadvertent program loop. This register is write-
only in 8-bit units (when it is read, undefined data is read out).
Writing to the first specific register (CKC or FLPMC register) is only valid after first writing to the PHCMD register.
Because of this, the register value can be overwritten only with the specified sequence, preventing an illegal write
operation from being performed.
7
6
PHCMD
REG7
REG6
Bit position
Bit name
7 to 0
REG7 to
REG0
The generation of an illegal store operation can be checked with the PRERR bit of the peripheral status register
(PHS).
302
CHAPTER 9 CLOCK GENERATION FUNCTION
) that is the same frequency as the internal clock frequency (f
XX
= 10 × f
) is used
XX
X
)
External Resonator or External Clock Frequency (f
XX
5.0000 MHz
4.0000 MHz
(4 to 5 MHz) value for which 10 × × × × f
X
, 2.5 × × × × f
, or 1 × × × × f
X
X
= 1 × f
, or f
).
X
XX
X
5
4
3
REG5
REG4
REG3
Registration Code (arbitrary 8-bit data)
The specific registers targeted are as follows.
• Clock control register (CKC)
• Flash programming mode control register (FLPMC)
User's Manual U14359EJ4V0UM
) (10 × f
) is generated, a system with low noise and
X
X
is used, a frequency of 4 to 6.6 MHz can be used.
X
2
1
0
REG2
REG1
REG0
Function
).
X
) (1 × f
X
)
X
does not exceed the system
X
XX
Address
After reset
FFFFF800H Undefined
) is
X
= 5 ×
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