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5.4.6 Refresh control function
The V850E/MA1 can generate a refresh cycle. The refresh cycle is set with SDRAM refresh control registers 1, 3,
4, and 6 (RFS1, RFS3, RFS4, RFS6). RFSn corresponds to CSn (n = 1, 3, 4, 6). For example, to connect SDRAM to
CS1, set RFS1.
When another bus master occupies the external bus, the DRAM controller cannot occupy the external bus. In this
case, the DRAM controller issues a refresh request to the bus master by changing the REFRQ signal to active (low
level).
During a refresh operation, the address bus retains the state it was in just before the refresh cycle.
(1) SDRAM refresh control registers 1, 3, 4, 6 (RFS1, RFS3, RFS4, RFS6)
These registers are used to enable or disable a refresh and set the refresh interval. The refresh interval is
determined by the following calculation formula.
Refresh interval ( µ s) = Refresh count clock (T
The refresh count clock and interval factor are determined by the RENn bit and RIN5n to RIN0n bits,
respectively, of the RFSn register.
Note that n corresponds to the register number (1, 3, 4, 6) of SDRAM configuration registers 1, 3, 4, 6 (SCR1,
SCR3, SCR4, SCR6).
These registers can be read/written in 16-bit units.
Caution Write to the RFS1, RFS3, RFS4, and RFS6 registers after reset, and then do not change the
set values. Also, do not access an external memory area other than the one for this
initialization routine until the initial settings of the RFS1, RFS3, RFS4, and RFS6 registers
are complete. However, it is possible to access external memory areas whose initialization
settings are complete.
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CHAPTER 5
MEMORY ACCESS CONTROL FUNCTION
RCY
User's Manual U14359EJ4V0UM
) × Interval factor
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