NEC V850E/MA1 User Manual page 506

15.3 Initialization
Initialize the contents of each register as necessary while programming.
The initial values of the CPU, internal RAM, and on-chip peripheral I/O after a reset are shown in Table 15-2.
Table 15-2. Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (1/3)
Internal Hardware
CPU Program registers
System registers
Internal RAM
On-chip Port functions
peripheral
I/O
Timer/counter
functions
506
CHAPTER 15 RESET FUNCTIONS
Register Name
General-purpose register (r0)
General-purpose registers (r1 to r31)
Program counter (PC)
Status saving registers during interrupt (EIPC, EIPSW)
Status saving registers during NMI (FEPC, FEPSW)
Interrupt source register (ECR)
Program status word (PSW)
Status saving registers during CALLT execution (CTPC, CTPSW)
Status saving registers during exception/debug trap (DBPC, DBPSW)
CALLT base pointer (CTBP)
Ports (P0 to P5, P7, PAL, PAH, PDL, PCS, PCT, PCM, PCD, PBD)
Mode registers (PM0 to PM5, PMCS, PMCT, PMCM, PMCD,
PMBD)
Mode registers (PMAL, PMAH, PMDL)
Mode control registers (PMC0, PMC1, PMC3 to PMC5, PMCBD)
Mode control register (PMC2)
Mode control registers (PMCAL, PMCDL)
Mode control register (PMCAH)
Mode control register (PMCCS)
Mode control register (PMCCT)
Mode control register (PMCCM)
Mode control register (PMCCD)
Function control registers (PFC0, PFC2 to PFC4, PFCCS, PFCCM,
PFCCD)
Timer Cn (TMCn) (n = 0 to 3)
Capture/compare registers Cn0 and Cn1 (CCCn0 and CCCn1)
(n = 0 to 3)
Timer mode control register Cn0 (TMCCn0) (n = 0 to 3)
Timer mode control register Cn1 (TMCCn1) (n = 0 to 3)
Timer Dn (TMDn) (n = 0 to 3)
Compare register (CMDn) (n = 0 to 3)
Timer mode control register Dn (n = 0 to 3)
User's Manual U14359EJ4V0UM
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Initial Value After Reset
00000000H
Undefined
00000000H
Undefined
Undefined
00000000H
00000020H
Undefined
Undefined
Undefined
Undefined
Undefined
FFH
FFFFH
00H
01H
0000H/FFFFH
0000H/03FFH
00H/FFH
00H/F3H
00H/3FH
00H/0FH
00H
0000H
0000H
00H
20H
0000H
0000H
00H