NEC V850E/MA1 User Manual page 432

(2) 4-buffer mode (external trigger select: 4 buffers)
In this mode, one analog input is A/D converted four times using the ADTRG signal as a trigger and the
results are stored in the ADCR0 to ADCR3 registers. The A/D conversion end interrupt (INTAD) is generated
and A/D conversion is stopped after the 4th A/D conversion.
Trigger
ADTRG signal
ADTRG signal
ADTRG signal
ADTRG signal
While the ADCE bit of the ADM0 register is 1, A/D conversion is repeated every time a trigger is input from
the ADTRG pin.
This mode is suitable for applications in which calculate the average of A/D conversion result is calculated.
Figure 12-16. Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers)
ADTRG
(1) The ADCE bit of ADM0 is set to 1 (enable)
(2) The external trigger is generated
(3) ANI2 is A/D converted
(4) The conversion result is stored in ADCR0
(5) The external trigger is generated
(6) ANI2 is A/D converted
(7) The conversion result is stored in ADCR1
432
CHAPTER 12
Analog Input A/D Conversion Result Register
ANIn ADCR0
ANIn ADCR1
ANIn ADCR2
ANIn ADCR3
ANI0
ANI1
(×4) (×4)
ANI2
ANI3
User's Manual U14359EJ4V0UM
A/D CONVERTER
A/D converter
(8) The external trigger is generated
(9) ANI2 is A/D converted
(10) The conversion result is stored in ADCR2
(11) The external trigger is generated
(12) ANI2 is A/D converted
(13) The conversion result is stored in ADCR3
(14) The INTAD interrupt is generated
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7