Table of Contents
Advertisement
(5) Successive approximation register (SAR)
The SAR is a 10-bit register that sets series resistor string voltage tap data, whose values match analog input
voltage values, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR all the way to the least significant bit (LSB) (A/D conversion completed), the contents
of the SAR (conversion results) are held in the A/D conversion result register (ADCRn). When all the
specified A/D conversion operations have been completed, an A/D conversion end interrupt (INTAD) occurs.
(6) A/D conversion result register (ADCRn)
ADCRn is a 10-bit register that holds A/D conversion results. Each time A/D conversion is completed, the
conversion results are loaded from the successive approximation register (SAR).
RESET input sets this register to 0000H.
(7) Controller
The controller selects the analog input, generates the sample & hold circuit operation timing, and controls the
conversion trigger according to the mode set by the ADM0 and ADM1 registers.
(8) ANI0 to ANI7 pins
These are 8-channel analog input pins for the A/D converter. They input the analog signals to be A/D
converted.
Caution Make sure that the voltages input to ANI0 to ANI7 do not exceed the rated values. If a
voltage higher than AV
maximum ratings) is input to a channel, the conversion value of the channel is undefined,
and the conversion values of the other channels may also be affected.
(9) AV
pin
REF
This is the pin for inputting the reference voltage of the A/D converter. It converts signals input to the ANIn
pin to digital signals based on the voltage applied between AV
In the V850E/MA1, the AV
voltage separately for the AV
CHAPTER 12
A/D CONVERTER
or lower than AV
DD
pin functions alternately as the AV
REF
pin and the AV
pin.
REF
DD
User's Manual U14359EJ4V0UM
(even within the range of the absolute
SS
and AV
.
REF
SS
pin. It is therefore impossible to set
DD
405
Advertisement
Table of Contents
