Chip Select Control Function - NEC V850E/MA1 User Manual

4.3.1 Chip select control function

Of the 256 MB memory area, the lower 8 MB (0000000H to 07FFFFFH) and the higher 8 MB (F800000H to
FFFFFFFH) can be divided into 2 MB memory blocks by chip area select control registers 0 and 1 (CSC0, CSC1) to
control the chip select signal.
The memory area can be effectively used by dividing it into memory blocks using the chip select control function.
The priority order is described below.
(1) Chip area select control registers 0, 1 (CSC0, CSC1)
These registers can be read/written in 16-bit units and become valid by setting each bit to 1.
If different chip select signal outputs are set to the same block, the priority order is controlled as follows.
CSC0: Peripheral I/O area > CS0 > CS2 > CS1
CSC1: Peripheral I/O area > CS7 > CS5 > CS6
If both the CS0n and CS2n bits of the CSC0 register are set to 0, CS1 is output to the corresponding block (n
= 0 to 3).
Similarly, if both the CS5n and CS7n bits of the CSC1 register are set to 0, CS6 is output to the
corresponding block (n = 0 to 3).
Caution Write to the CSC0 and CSC1 registers after rest, and then do not change the set value.
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CHAPTER 4 BUS CONTROL FUNCTION
User's Manual U14359EJ4V0UM