NEC V850E/MA1 User Manual page 134

(4) EDO DRAM (when written, when bus hold request acknowledged during on-page access)
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
WAIT (input)
Notes 1. TRPW and TCPW are always inserted for 1 or more cycles.
2. This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
4. Timing from DRAM access to bus hold state.
134
CHAPTER 4 BUS CONTROL FUNCTION
Note 1
TRPW T1 T2 TCPW
Row Column
address address
Data
indicates the sampling timing.
User's Manual U14359EJ4V0UM
Note 1 Note 2
TB TI TH
Column
address
Data
Off-page
cycle
Note 2 Note 1
TH TI TRPW
Undefined