Table of Contents
Advertisement
Figure 5-2. SRAM, External ROM, External I/O Access Timing (5/6)
CLKOUT (output)
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
WAIT (input)
Note When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
148
CHAPTER 5
MEMORY ACCESS CONTROL FUNCTION
(e) For read → → → → write operation
T1
RD (output)
OE (output)
Note
Note
indicates the sampling timing.
User's Manual U14359EJ4V0UM
T2
T1
Address
Address
Data
T2
Data
Advertisement
Table of Contents
