NEC V850E/MA1 User Manual page 246

Figure 6-16. Timing of Flyby Transfer (DRAM → → → → External I/O) (2/3)
TI TI
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
A0 to A25 (output)
D0 to D15 (I/O)
RASm (output) of
DRAM area
CSn (output) of
external I/O area
BCYST (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
WAIT (input)
Note TRPW is always inserted for one or more cycles.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 (n ≠ m)
4. Col.: Column address
Row: Row address
246
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
(b) Single transfer mode
Note
TRPW T1 T2
TI TI TO T1FH T2FH T1FH TF
Row
Col.
Data
indicates the sampling timing.
User's Manual U14359EJ4V0UM
TE TI TI TI TI TI TI
Note
TRPW T1 T2
TO T1FH T2FH T2FH TF TE
Row
Col.
Data