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Figure 6-10. Timing of 2-Cycle DMA Transfer (External I/O → → → → SRAM)
TI
TI
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
A0 to A25 (output)
D0 to D15 (I/O)
CSm (output) of
external I/O area
CSn (output) of
SRAM area
BCYST (output)
RD (output)
H
OE (output)
H
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
Note 2
IORD (output)
Note 2
IOWR (output)
WAIT (input)
Notes 1.
This idle state (TI) is independent of the BCC register setting.
2.
When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 0 to 7, x = 0 to 3 (n ≠ m)
CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
(a) Single-step transfer mode
T1
T2
T1
TI
TI
TI
TO
T1R
T2R
T1W
Note 1
Address
Address
Data
indicates the sampling timing.
User's Manual U14359EJ4V0UM
T2
T1
TW
T2W
TI
TI
TI
TO
T1R
T2R
Address
Data
T2
T1
TW
T2
TI
T2R
T1W
T2W
T2W
Note 1
Address
Data
Data
231
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