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Self-programming function ..................................... 522
SELFREF ................................................................. 54
Self-refresh control function (EDO DRAM)............. 175
Self-refresh control function (SDRAM) ................... 201
Serial I/O shift registers 0 to 2 ................................ 396
SESC0 to SESC3........................................... 286, 333
SI0, SI1 .................................................................... 51
SI2............................................................................ 50
Single transfer mode .............................................. 224
Single-step transfer mode ...................................... 226
SIO0 to SIO2.......................................................... 396
SIOE0 to SIOE2 ..................................................... 397
SO0, SO1................................................................. 51
SO2.......................................................................... 50
Software exception................................................. 288
Software STOP mode ............................................ 317
SOTB0 to SOTB2................................................... 398
Specific registers...................................................... 94
SRAM connection .................................................. 142
SRAM, external ROM, external I/O access ............ 144
SRAM, external ROM, external I/O interface ......... 141
SRIC0 to SRIC2 ..................................................... 281
STIC0 to STIC2...................................................... 281
Stopping conversion operation............................... 435
Switching between UART and CSI modes............. 358
System configuration example (CSI0 to SCI2) ....... 403
System register set .................................................. 68
System wait control register ..................................... 94
[T]
TBC........................................................................ 322
TC0 to TC3 .............................................................. 49
Terminal count output upon DMA transfer end ...... 259
TI000........................................................................ 47
TI010........................................................................ 48
TI020........................................................................ 49
TI030........................................................................ 52
Time base counter ................................................. 322
Timer C .................................................................. 323
Timer C operation .................................................. 334
Timer D .................................................................. 349
Timer D operation .................................................. 355
Timer mode control registers C00 to C30 .............. 329
Timer mode control registers C01 to C31 .............. 331
Timer mode control registers D0 to D3 .................. 353
Timers C0 to C3 ..................................................... 325
Timers D0 to D3 ..................................................... 350
Times related to DMA transfer ............................... 261
566
APPENDIX C INDEX
TMC0 to TMC3 ...................................................... 325
TMCC00 to TMCC30 ............................................. 329
TMCC01 to TMCC31 ............................................. 331
TMCD0 to TMCD3 ................................................. 353
TMD0 to TMD3 ...................................................... 350
TO00........................................................................ 47
TO01........................................................................ 48
TO02........................................................................ 49
TO03........................................................................ 52
Total error .............................................................. 437
Transfer modes ..................................................... 224
Transfer object....................................................... 255
Transfer type and transfer object........................... 255
Transfer types........................................................ 228
Transmit buffer registers 0 to 2.............................. 368
2-cycle transfer ...................................................... 228
TXB0 to TXB2........................................................ 368
TXD0, TXD1 ............................................................ 51
TXD2 ....................................................................... 50
Types of bus states................................................ 221
[U]
UART0 to UART2 .................................................. 359
UBE ......................................................................... 58
UCAS....................................................................... 55
UDQM...................................................................... 55
UWR ........................................................................ 55
[V]
Valid edge selection registers C0 to C3..........286, 333
V
........................................................................... 60
DD
V
........................................................................... 61
PP
V
........................................................................... 60
SS
VSWC...................................................................... 94
[W]
WAIT........................................................................ 53
Wait function.......................................................... 119
WE........................................................................... 56
Wrap-around of CPU address space ....................... 74
Writing by flash programmer.................................. 509
[X]
X1, X2...................................................................... 60
[Z]
Zero-scale error ..................................................... 438
User's Manual U14359EJ4V0UM
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