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SDCLK (output)
A10 (output)
A0 to A9, A11 to A23
(output)
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
H
LDQM (output)
H
UDQM (output)
D0 to D15 (I/O)
SDCKE (output)
Note Shown above is the case when the self-refresh cycle is started in the IDLE or software STOP mode. If
the self-refresh cycle is started by inputting the active level of the SELFREF signal, SDCLK is output
without going low.
Remarks 1. The number of wait states set by the BCW1n and BCW0n bits of the SCRn register × 4 clocks
will be inserted in the BCW × 4 clk period.
2. n = 1, 3, 4, 6
202
CHAPTER 5
MEMORY ACCESS CONTROL FUNCTION
Figure 5-19. Self-Refresh Timing (SDRAM)
TW
TW NOP
TREF
TW
Note
User's Manual U14359EJ4V0UM
BCW × 4clk
TW
TW
TW
TW
TDCW TDCW
TDCW
TDCW
TI
TI
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