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Figure 6-12. Timing of 2-Cycle DMA Transfer (EDO DRAM → → → → SRAM) (2/3)
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Address (output)
BCYST (output)
CSn (output) of
SRAM area
RASm (output) of
DRAM area
CSn (output) of
other area
LCAS/LWR (output)
UCAS/UWR (output)
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Notes 1.
TRPW is always inserted for one or more cycles.
2.
In the case of the RAS hold mode
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
4. Col.: Column address
Row: Row address
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CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
(b) Single-step transfer mode
Note 1
T1
T2
T1
T2
TRPW
T1
TI
TI
TI
TI
TO
T1R
T2R T2R
Row
Data
Data
indicates the sampling timing.
User's Manual U14359EJ4V0UM
T2
T1
T2
T1
T2
T1
TE
T1W
T2W
TI
TI
TI
Col.
Address
Note 2
Data
Data
Data
Data
T2
TB
T1
T2
TI
T1R
TE
T1W
T2W
Col.
Address
Data
Data
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