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(b) Baud rate generator control registers 0 to 2 (BRGC0 to BRGC2)
The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn.
These registers can be read or written in 8-bit units.
Caution If the BRGn7 to BRGn0 bits are to be overwritten, TXEn and RXEn should be set to 0
in the ASIMn register first (n = 0 to 2).
7
6
BRGC0
MDL07
MDL06
BRGC1
MDL17
MDL16
BRGC2
MDL27
MDL26
Bit position
Bit name
7 to 0
BRGn7 to
BRGn0
(n = 0 to 2)
Remarks 1. f
: Frequency of clock selected according to TPSn3 to TPSn0 bits of CKSRn register.
XCLK
2. k: Value set according to BRGn7 to BRGn0 bits (k = 8, 9, 10, ..., 255)
3. x: don't care
384
CHAPTER 11 SERIAL INTERFACE FUNCTION
5
4
3
MDL05
MDL04
MDL03
MDL15
MDL14
MDL13
MDL25
MDL24
MDL23
Specifies the 8-bit counter's divisor value.
B R G n 7 B R G n 6 B R G n 5 B R G n 4 B R G n 3 B R G n 2 B R G n 1 B R G n 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
User's Manual U14359EJ4V0UM
2
1
0
MDL02
MDL01
MDL00
MDL12
MDL11
MDL10
MDL22
MDL21
MDL20
Function
value (k)
0
0
x
x
x
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
Address
After reset
FFFFFA07H
FFH
FFFFFA17H
FFH
FFFFFA27H
FFH
Divisor
Serial clock
−
Setting
prohibited
8
f
/8
XCLK
9
f
/9
XCLK
10
f
/10
XCLK
250
f
/250
XCLK
251
f
/251
XCLK
252
f
/252
XCLK
253
f
/253
XCLK
254
f
/254
XCLK
255
f
/255
XCLK
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