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(2) Serial clock generation
A serial clock can be generated according to the settings of the CKSRn and BRGCn registers (n = 0 to 2).
The clock input to the 8-bit counter is selected according to the TPSn3 to TPSn0 bits of the CKSRn register.
The 8-bit counter divisor value can be selected according to the BRGn7 to BRGn0 bits of the BRGCn
register.
(a) Clock select registers 0 to 2 (CKSR0 to CKSR2)
The CKSRn register is an 8-bit register for selecting the input block according to the TPSn3 to TPSn0
bits. The clock selected by the TPSn3 to TPSn0 bits becomes the basic clock of the transmission/
reception module. Its frequency is referred to as f
These registers can be read or written in 8-bit units.
Cautions 1. The maximum allowable frequency of the basic clock (f
when the system clock's frequency is 50 MHz, bits TPSn3 to TPSn0 cannot be set to
0000B (n = 0 to 2).
If the system clock frequency is 50 MHz, set the TPSn3 to TPSn0 bits to a value
other than 0000B and set the UARTCAEn bit of the ASIMn register to 1.
2. If the TPSn3 to TPSn0 bits are to be overwritten, the UARTCAEn bit of the ASIMn
register should be set to 0 first.
7
6
CKSR0
0
0
CKSR1
0
0
CKSR2
0
0
Bit position
Bit name
3 to 0
TPSn3 to
TPSn0
(n = 0 to 2)
Remark f
: Internal system clock
XX
CHAPTER 11 SERIAL INTERFACE FUNCTION
5
4
3
0
0
TPS03
TPS02
0
0
TPS13
TPS12
0
0
TPS23
TPS22
Specifies the basic clock.
TPSn3
TPSn2
TPSn1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
Arbitrary Arbitrary Setting prohibited
User's Manual U14359EJ4V0UM
.
XCLK
2
1
0
TPS01
TPS00
TPS11
TPS10
TPS21
TPS20
Function
TPSn0
Basic clock (f
0
0
f
XX
0
1
f
/2
XX
1
0
f
/4
XX
1
1
f
/8
XX
0
0
f
/16
XX
0
1
f
/32
XX
1
0
f
/64
XX
1
1
f
/128
XX
0
0
f
/256
XX
0
1
f
/512
XX
1
0
f
/1,024
XX
1
1
f
/2,048
XX
) is 25 MHz. Therefore,
XCLK
Address
After reset
FFFFFA06H
00H
FFFFFA16H
00H
FFFFFA26H
00H
)
XCLK
383
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