NEC V850E/MA1 User Manual page 241

Figure 6-14. Timing of 2-Cycle DMA Transfer (SDRAM → → → → SRAM) (1/3)
T1 T2
TI TI TI
SDCLK (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Address (output)
BCYST (output)
CSn (output) of
SRAM area
CSn (output) of
SDRAM area
CSn (output) of
other area
SDRAS (output)
SDCAS (output)
RD (output)
WE (output)
LDQM/LWR (output)
UDQM/UWR (output)
D0 to D15 (I/O) Data
SDCKE (output)
H
Note This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, x = 0 to 3
4. Col.: Column address
Row: Row address
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
(a) Single transfer mode
T1 T2 TW TACT TREAD TLATE TLATE
Note
TI TO T1R T2R T2R T2R T2R TI
Row
Col.
Data Data
indicates the sampling timing.
User's Manual U14359EJ4V0UM
T1 T2 T1 TW T2 T1 TW T2
T1W T2W TI TI TI TI TI TO
Address
Data Data Data
TW TREAD TLATE TLATE T1 T2
Note
T1W T2W T2W T2W TI T1R T2R
Col. Address
Data Data
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