NEC V850E/MA1 User Manual page 285

32-bit single-chip microcontroller

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Table of Contents

CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION

ES1131 ES1130

ES1231 ES1230

INTP123/ADTRG

ES1331 ES1330

Bit position

(n = 0 to 3,

The level of the INTP1nm pin is sampled at the interval of the system clock divided by two, and the

P1nIFm bit is latched as an interrupt request when a low level is detected. Therefore, even if the

P1nIFm bit of the interrupt control register (P1nICm) is automatically cleared to 0 when the CPU

acknowledges an interrupt, the P1nIFm bit is immediately set to 1, and an interrupt is generated

continuously. To avoid this, forcibly clear the P1nIFm bit to 0 after making the INTP1nm pin

inactive for an external device in the interrupt service routine (n = 0 to 3, m = 0 to 3).

When a lower priority level-detection interrupt request (INTP1nm) occurs while another interrupt is

being serviced and this newly generated level-detection interrupt request becomes inactive before

the current interrupt service is complete, this new interrupt request (INTP1nm) is held pending. To

avoid acknowledging this INTP1nm interrupt request, clear the P1nIFm bit of the interrupt control

When this pin is used as the ADTRG pin, do not select this setting (level detection).

ES1121 ES1120

ES1111 ES1110

ES1221 ES1220

ES1211 ES1210

ES1321 ES1320

ES1311 ES1310

Specifies the valid edge of the INTP1nm and ADTRG pins.

User's Manual U14359EJ4V0UM

Falling edge

Level detection (low-level detection)

Both rising and falling edges

Notes 1, 2, 3