NEC V850E/MA1 User Manual page 362

11.2.3 Control registers
(1) Asynchronous serial interface mode registers 0 to 2 (ASIM0 to ASIM2)
These are 8-bit registers for controlling the transfer operations of UART0 to UART2.
These registers can be read or written in 8-bit or 1-bit units.
Caution When using UARTn, set the external pins related to the UARTn function in the control
mode, set clock select register n (CKSRn) and baud rate generator control register n
(BRGCn). Then set the UARTCAEn bit to 1 before setting the other bits.
<7> <6>
ASIM0 TXE0
UARTCAE0
ASIM1 TXE1
UARTCAE1
ASIM2 TXE2
UARTCAE2
Bit position Bit name
7 UARTCAEn
(n = 0 to 2)
6 TXEn
(n = 0 to 2)
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CHAPTER 11 SERIAL INTERFACE FUNCTION
<5> 4 3
RXE0 PS01 PS00
RXE1 PS11 PS10
RXE2 PS21 PS20
Clock Enable
Controls the operation clock (n = 0 to 2).
0: Stops supply of clocks to UARTn unit
1: Supplies clocks to UARTn unit
Cautions 1. When the UARTCAEn bit is set to 0, the UARTn unit can be
asynchronously reset.
2. When UARTCAEn = 0, the UARTn unit is in a reset state.
Therefore, to operate UARTn, the UARTCAEn bit must be set to
1.
3. When the UARTCAEn bit is changed from 1 to 0, all registers of
the UARTn unit are initialized. When the UARTCAEn is set to 1
again, the UARTn unit registers must be set again.
The TXDn pin output is always high level in the transmission disable state,
irrespective of the setting of the UARTCAEn bit.
Transmit Enable
Specifies whether transmission is enabled or disabled.
0: Transmission is disabled
1: Transmission is enabled
Cautions 1. On startup, set UARTCAEn to 1 and then set TXEn to 1. To
stop transmission, clear TXEn to 0 and then UARTCAEn to 0.
2. When the transmission unit status is to be initialized, the
transmission status may not be able to be initialized unless the
TXEn bit is set (1) again after an interval of two cycles of the
basic clock has elapsed since the TXEn bit was cleared (0) (For
the basic clock, see 11.2.6 (1) (a) Basic clock (Clock)).
User's Manual U14359EJ4V0UM
2 1 0
CL0 SL0 ISRM0 FFFFFA00H
CL1 SL1 ISRM1 FFFFFA10H
CL2 SL2 ISRM2 FFFFFA20H
Function
(1/3)
Address After reset
01H
01H
01H