NEC V850E/MA1 User Manual page 194

(c) Write timing (16-bit bus width word access, bank change, BCW = 1, latency = 2)
SDCLK (output)
Note (output)
Bank address (output)
A11 (output)
A0 to A10 (output)
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
D0 to D15 (I/O)
SDCKE (Output)
H
Note Addresses other than the bank address, A11, and A0 to A10.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
4. Add.: Address
Bnk.: Bank address
Col.: Column address
Row: Row address
194
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
Figure 5-16. SDRAM Access Timing (3/4)
Bank A write
TW TACT TWR TWR TWPRE TWE TW
BCW
Add. Add.
Add. Bnk. Add. Bnk.
Add.
Add. Row Add. Row
Add.
Add. Row Col. Col. Add.
Data Data
indicates the sampling timing.
User's Manual U14359EJ4V0UM
Bank B write
TACT TWR TWR TWPRE TWE TW
BCW
Add. Add.
Bnk. Add.
Add.
Add.
Add.
Row Col. Col.
Data Data
Bank B write
TW TWR TWR TWPRE TWE
Add. Add.
Add.
Add.
Col. Col.
Data Data
When write-accessing the page
that includes bank B, which was
accessed by the previous write
access.