Noise Elimination Circuit; Figure 8-14: Port Interrupt Input Circuit (P52, P53, P61, P62, P63, P64); Figure 8-15: Timer G Input Circuit (P30, P35, P40, P45, P54, P55); Figure 8-16: Nmi Input Circuit - NEC V850E/CA2 JUPITER Preliminary User's Manual

8.4 Noise Elimination Circuit

V850E/CA2 is provided with input filter for noise suppression for ports P3 to P5 and on all interrupt and
timer G, timer C control inputs. For peripheral interrupts, programmable edge detection is available.
Inputs for Timer G are equipped with edge detection and need only noise suppression.

Figure 8-14: Port Interrupt Input Circuit (P52, P53, P61, P62, P63, P64)

Input

Figure 8-15: Timer G Input Circuit (P30, P35, P40, P45, P54, P55)

Input
Input
Note: Edge select circuit is different for NMI and INTPn. NMI can only configured as rising or falling
edge sensitive whereas INTPn can be triggered by rising, falling or both edges.
Chapter 8 Interrupt/Exception Processing Function
Noise Filter
Noise Filter

Figure 8-16: NMI Input Circuit

Noise Filter
Preliminary User's Manual U15839EE1V0UM00
Edge Detect
INT (CPU)
ESn1 ESn0
TInm (TMC, TMG)
Edge Detect
INT (CPU)
ESn1 ESn0
Edge Detect
INT (CPU)
ESn0
221