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6.9 Next Address Setting Function
The DMA source address registers (DSAnH, DSAnL), DMA destination address registers (DDAnH, DDAnL), and
DMA transfer count register (DBCn) are buffer registers with a 2-stage FIFO configuration (n = 0 to 3).
When the terminal count is issued, these registers are automatically rewritten with the value that was set immediately
before.
Therefore, during DMA transfer, transfer is automatically started when a new DMA transfer setting is made for
these registers and the Enn bit of the DCHCn register, and MLEn bit is set to 1 (however, the DMA transfer end
interrupt may be issued even if DMA transfer is automatically started).
Figure 6-20 shows the configuration of the buffer register.
CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-20. Buffer Register Configuration
Data read
Data write
Master
register
User's Manual U14359EJ4V0UM
Address/
Slave
count
register
controller
257
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