NEC V850E/MA1 User Manual page 192

(a) Read timing (16-bit bus width word access, page change, BCW = 2, latency = 2)
SDCLK (output)
Note (output)
Bank address (output)
A11 (output)
A0 to A10 (output)
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
D0 to D15 (I/O)
SDCKE (output)
Note Addresses other than the bank address, A11, and A0 to A10.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
4. Add.: Address
Bnk.: Bank address
Col.: Column address
Row: Row address
192
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
Figure 5-16. SDRAM Access Timing (1/4)
TW TACT TBCW TREAD TREAD TLATE
BCW
Add. Add.
Add. Bnk.
Add.
Add. Row
Add.
Add. Col.
Row
H
indicates the sampling timing.
User's Manual U14359EJ4V0UM
TLATE TW TPREC TBCW TACT TBCW
BCW
Add.
Add. Bnk. Add. Bnk.
Add. Add. Row
Col. Add. Row
Data Data
TREAD TREAD TLATE TLATE
BCW
Add.
Add.
Col.
Col.
Data Data