NEC V850E/MA1 User Manual page 335

32-bit single-chip microcontroller

Hide thumbs Also See for V850E/MA1:

Table of Contents

CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)

(2) Overflow

When the TMCn register has counted the count clock from FFFFH to 0000H, the OVFn bit of the TMCCn0

if the CCCn0 register is set to compare mode (CMSn0 bit = 1) and to the value FFFFH when match clearing

is enabled (CCLRn bit = 1), then the TMCn register is considered to be cleared and the OVFn bit is not set (1)

when the TMCn register changes from FFFFH to 0000H. Also, the overflow interrupt (INTOV0n) is not

When the TMCn register is changed from FFFFH to 0000H because the TMCCEn bit changes from 1 to 0,

the TMCn register is considered to be cleared, but the OVFn bit is not set (1) and no INTOV0n interrupt is

Also, timer operation can be stopped after an overflow by setting the OSTn bit of the TMCCn1 register to 1.

When the timer is stopped due to an overflow, the count operation is not restarted until the TMCCEn bit of the

TMCCn0 register is set (1).

Operation is not affected even if the TMCCEn bit is set (1) during a count operation.

Figure 10-2. Operation After Overflow (When OSTn = 1)

User's Manual U14359EJ4V0UM