NEC V850E/MA1 User Manual page 176

CLKOUT (output)
REFRQ (output)
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
WAIT (input)
Notes 1. Shown above is the case when the self-refresh cycle is started in the IDLE or software STOP mode.
If the self-refresh cycle is started by inputting the active level of the SELFREF signal, CLKOUT is
output without going low.
2. The TRCW cycle is always inserted for one or more clocks, irrespective of the setting of bits RCW2
to RCW0 of the RWC register.
Remarks 1. This timing is obtained when the bits of the RWC register have the following settings.
RRW1, RRW0 = 01B:
RCW2 to RCW0 = 001B: 1 wait (TRCW)
SRW2 to SRW0 = 001B: 1 wait (TSRW) (double the number of wait states than the set value will be
inserted)
2. n = 0 to 7, m = 1, 3, 4, 6
176
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
Figure 5-10. Self-Refresh Timing (DRAM)
TRRW
1 wait (TRRW)
User's Manual U14359EJ4V0UM
TRCW
Note 2
Note 1
TSRW TSRW